232 lines
7.3 KiB
Tcl
232 lines
7.3 KiB
Tcl
# Test disable timing, case analysis, logic values, data checks
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# Targets: Sdc.cc (setDisableTiming, case analysis, logic values,
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# setDataCheck, removeDataCheck, clockGatingMargin*),
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# DisabledPorts.cc, DataCheck.cc,
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# WriteSdc.cc (writeDisables, writeCaseAnalysis, writeConstants,
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# writeDataChecks, writeClockGatingCheck)
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source ../../test/helpers.tcl
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read_liberty ../../test/nangate45/Nangate45_typ.lib
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read_verilog sdc_test2.v
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link_design sdc_test2
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# Setup
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create_clock -name clk1 -period 10 [get_ports clk1]
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create_clock -name clk2 -period 20 [get_ports clk2]
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set_input_delay -clock clk1 2.0 [get_ports in1]
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set_input_delay -clock clk1 2.0 [get_ports in2]
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set_input_delay -clock clk2 2.0 [get_ports in3]
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set_output_delay -clock clk1 3.0 [get_ports out1]
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set_output_delay -clock clk2 3.0 [get_ports out2]
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############################################################
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# Disable timing - instances
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############################################################
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set_disable_timing [get_cells buf1]
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set_disable_timing [get_cells inv1]
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set_disable_timing [get_cells and1]
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report_checks
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# Unset and re-enable
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unset_disable_timing [get_cells buf1]
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unset_disable_timing [get_cells inv1]
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unset_disable_timing [get_cells and1]
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############################################################
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# Disable timing - pins
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############################################################
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set_disable_timing [get_pins buf1/A]
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set_disable_timing [get_pins inv1/A]
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set_disable_timing [get_pins and1/A1]
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report_checks
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unset_disable_timing [get_pins buf1/A]
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unset_disable_timing [get_pins inv1/A]
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unset_disable_timing [get_pins and1/A1]
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############################################################
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# Disable timing - lib cells
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############################################################
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set_disable_timing [get_lib_cells NangateOpenCellLibrary/BUF_X1]
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set_disable_timing [get_lib_cells NangateOpenCellLibrary/INV_X1] -from A -to ZN
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set_disable_timing [get_lib_cells NangateOpenCellLibrary/NAND2_X1] -from A1 -to ZN
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set_disable_timing [get_lib_cells NangateOpenCellLibrary/NOR2_X1]
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set_disable_timing [get_lib_cells NangateOpenCellLibrary/AND2_X1] -from A1 -to ZN
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# Write SDC with disable timing
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set sdc_file1 [make_result_file sdc_disable1.sdc]
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write_sdc -no_timestamp $sdc_file1
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diff_files sdc_disable1.sdcok $sdc_file1
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# Unset all lib cell disables
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unset_disable_timing [get_lib_cells NangateOpenCellLibrary/BUF_X1]
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unset_disable_timing [get_lib_cells NangateOpenCellLibrary/INV_X1] -from A -to ZN
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unset_disable_timing [get_lib_cells NangateOpenCellLibrary/NAND2_X1] -from A1 -to ZN
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unset_disable_timing [get_lib_cells NangateOpenCellLibrary/NOR2_X1]
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unset_disable_timing [get_lib_cells NangateOpenCellLibrary/AND2_X1] -from A1 -to ZN
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############################################################
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# Case analysis
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############################################################
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# case_analysis 0
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set_case_analysis 0 [get_ports in1]
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# case_analysis 1
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set_case_analysis 1 [get_ports in2]
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# case_analysis rising
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set_case_analysis rising [get_ports in3]
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report_checks
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# Write SDC with case analysis (exercises writeCaseAnalysis)
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set sdc_file2 [make_result_file sdc_case1.sdc]
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write_sdc -no_timestamp $sdc_file2
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diff_files sdc_case1.sdcok $sdc_file2
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# Unset case analysis
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unset_case_analysis [get_ports in1]
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unset_case_analysis [get_ports in2]
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unset_case_analysis [get_ports in3]
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# case_analysis falling
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set_case_analysis falling [get_ports in1]
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set sdc_file3 [make_result_file sdc_case2.sdc]
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write_sdc -no_timestamp $sdc_file3
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diff_files sdc_case2.sdcok $sdc_file3
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unset_case_analysis [get_ports in1]
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############################################################
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# Logic values (set_logic_zero, set_logic_one, set_logic_dc)
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############################################################
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set_logic_zero [get_ports in1]
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set_logic_one [get_ports in2]
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# set_logic_dc (don't care)
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set_logic_dc [get_ports in3]
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# Write SDC with logic values (exercises writeConstants)
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set sdc_file4 [make_result_file sdc_logic1.sdc]
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write_sdc -no_timestamp $sdc_file4
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diff_files sdc_logic1.sdcok $sdc_file4
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report_checks
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############################################################
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# Data checks
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############################################################
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set_data_check -from [get_pins reg1/Q] -to [get_pins reg2/D] -setup 0.5
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set_data_check -from [get_pins reg1/Q] -to [get_pins reg2/D] -hold 0.3
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set_data_check -rise_from [get_pins reg1/Q] -to [get_pins reg2/D] -setup 0.6
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set_data_check -from [get_pins reg1/Q] -fall_to [get_pins reg2/D] -hold 0.25
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# Write with data checks
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set sdc_file5 [make_result_file sdc_datacheck1.sdc]
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write_sdc -no_timestamp $sdc_file5
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diff_files sdc_datacheck1.sdcok $sdc_file5
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# Remove data checks
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unset_data_check -from [get_pins reg1/Q] -to [get_pins reg2/D] -setup
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unset_data_check -from [get_pins reg1/Q] -to [get_pins reg2/D] -hold
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############################################################
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# Clock gating check (exercises clockGatingMargin paths)
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############################################################
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# Design-level
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set_clock_gating_check -setup 0.5
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set_clock_gating_check -hold 0.3
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# Clock-level
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set_clock_gating_check -setup 0.4 [get_clocks clk1]
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set_clock_gating_check -hold 0.2 [get_clocks clk1]
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set_clock_gating_check -setup 0.35 [get_clocks clk2]
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set_clock_gating_check -hold 0.15 [get_clocks clk2]
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# Instance-level
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set_clock_gating_check -setup 0.3 [get_cells reg1]
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set_clock_gating_check -hold 0.1 [get_cells reg1]
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# Pin-level
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set_clock_gating_check -setup 0.25 [get_pins reg1/CK]
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set_clock_gating_check -hold 0.08 [get_pins reg1/CK]
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# Write SDC with clock gating
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set sdc_file6 [make_result_file sdc_clkgate1.sdc]
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write_sdc -no_timestamp $sdc_file6
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diff_files sdc_clkgate1.sdcok $sdc_file6
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############################################################
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# set_ideal_network / set_ideal_transition
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############################################################
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set_ideal_network [get_ports clk1]
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set_ideal_network [get_ports clk2]
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set_ideal_transition 0.0 [get_ports clk1]
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set_ideal_transition 0.05 [get_ports clk2]
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############################################################
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# Min pulse width on various objects
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############################################################
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set_min_pulse_width 1.0 [get_clocks clk1]
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set_min_pulse_width -high 0.6 [get_clocks clk1]
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set_min_pulse_width -low 0.4 [get_clocks clk1]
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set_min_pulse_width 0.8 [get_clocks clk2]
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set_min_pulse_width 0.5 [get_pins reg1/CK]
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set_min_pulse_width 0.6 [get_cells reg1]
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############################################################
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# Latch borrow limits on various objects
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############################################################
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set_max_time_borrow 2.0 [get_clocks clk1]
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set_max_time_borrow 1.5 [get_clocks clk2]
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set_max_time_borrow 1.0 [get_pins reg1/D]
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set_max_time_borrow 1.2 [get_cells reg2]
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############################################################
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# Comprehensive write with all constraints
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############################################################
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set sdc_final [make_result_file sdc_disable_case_final.sdc]
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write_sdc -no_timestamp $sdc_final
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diff_files_sorted sdc_disable_case_final.sdcok $sdc_final
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set sdc_compat [make_result_file sdc_disable_case_compat.sdc]
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write_sdc -no_timestamp -compatible $sdc_compat
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diff_files_sorted sdc_disable_case_compat.sdcok $sdc_compat
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set sdc_d6 [make_result_file sdc_disable_case_d6.sdc]
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write_sdc -no_timestamp -digits 6 $sdc_d6
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diff_files_sorted sdc_disable_case_d6.sdcok $sdc_d6
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report_checks
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