154 lines
4.3 KiB
Tcl
154 lines
4.3 KiB
Tcl
# Test port external capacitance, set_load with rise/fall/min/max/corner,
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# capacitance limits on cell/port/pin, propagated clock set/unset,
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# and unset_case_analysis from various pin states.
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# Targets:
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# Sdc.cc: setPortExtPinCap, setPortExtWireCap, portExtCap (all overloads),
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# hasPortExtCap, portExtFanout, ensurePortExtPinCap,
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# setCapacitanceLimit(Cell/Port/Pin), capacitanceLimit(Port/Pin),
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# setPropagatedClock, removePropagatedClock (clock and pin),
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# removeCaseAnalysis, setCaseAnalysis (all 4 values),
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# unsetCaseAnalysis, setLogicValue,
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# setPortExtFanout, portExtFanout (int overload),
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# connectedPinCap (via set_load -subtract_pin_load),
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# findLeafLoadPins, findLeafDriverPins (via input_delay on ports)
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# WriteSdc.cc: writePortLoads (pin/wire/fanout writing),
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# writeCaseAnalysis (all values), writeConstants,
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# writePropagatedClkPins, writeCapacitanceLimits
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# PortExtCap.cc: pinCap, wireCap, fanout methods
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source ../../test/helpers.tcl
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read_liberty ../../test/nangate45/Nangate45_typ.lib
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read_verilog sdc_test2.v
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link_design sdc_test2
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create_clock -name clk1 -period 10 [get_ports clk1]
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create_clock -name clk2 -period 20 -waveform {0 10} [get_ports clk2]
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set_input_delay -clock clk1 2.0 [get_ports in1]
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set_input_delay -clock clk1 2.0 [get_ports in2]
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set_input_delay -clock clk2 2.0 [get_ports in3]
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set_output_delay -clock clk1 3.0 [get_ports out1]
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set_output_delay -clock clk2 3.0 [get_ports out2]
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# Test 1: set_load - basic pin and wire loads
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set_load 0.05 [get_ports out1]
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set_load -pin_load 0.04 [get_ports out1]
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set_load -wire_load 0.02 [get_ports out1]
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set_load -pin_load 0.03 [get_ports out2]
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# Test 2: set_load with rise/fall
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set_load -pin_load -rise 0.045 [get_ports out1]
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set_load -pin_load -fall 0.055 [get_ports out1]
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set_load -wire_load -rise 0.015 [get_ports out2]
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set_load -wire_load -fall 0.025 [get_ports out2]
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# Test 3: set_load with min/max
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set_load -min 0.01 [get_ports out1]
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set_load -max 0.06 [get_ports out1]
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set_load -pin_load -min 0.02 [get_ports out2]
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set_load -pin_load -max 0.05 [get_ports out2]
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# Test 4: Port fanout number
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set_port_fanout_number 4 [get_ports out1]
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set_port_fanout_number 8 [get_ports out2]
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# Test 5: Net wire cap (set_load on nets)
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set_load 0.01 [get_nets n1]
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set_load 0.02 [get_nets n2]
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# Test 6: Capacitance limits
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# Design-level
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set_max_capacitance 0.25 [current_design]
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# Port-level
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set_max_capacitance 0.15 [get_ports out1]
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set_max_capacitance 0.20 [get_ports out2]
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set_min_capacitance 0.01 [get_ports out1]
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set_min_capacitance 0.005 [get_ports out2]
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# Pin-level
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set_max_capacitance 0.10 [get_pins reg1/D]
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# Transition limits
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set_max_transition 0.5 [current_design]
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set_max_transition 0.3 [get_ports out1]
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set_max_transition -clock_path 0.2 [get_clocks clk1]
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set_max_transition -data_path 0.4 [get_clocks clk1]
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# Fanout limits
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set_max_fanout 20 [current_design]
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set_max_fanout 10 [get_ports in1]
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set_max_area 200.0
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# Write with all capacity/load constraints
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set sdc1 [make_result_file sdc_cap_prop1.sdc]
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write_sdc -no_timestamp $sdc1
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# Test 7: Propagated clocks - set and unset
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# Set propagated on clock object
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set_propagated_clock [get_clocks clk1]
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# Set propagated on port (pin)
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set_propagated_clock [get_ports clk2]
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# Write with propagated
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set sdc2 [make_result_file sdc_cap_prop2.sdc]
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write_sdc -no_timestamp $sdc2
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# Unset propagated on clock
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unset_propagated_clock [get_clocks clk1]
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# Unset propagated on pin
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unset_propagated_clock [get_ports clk2]
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# Verify propagated is removed
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set sdc3 [make_result_file sdc_cap_prop3.sdc]
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write_sdc -no_timestamp $sdc3
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# Test 8: Case analysis - all 4 values and unset
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# Value 0
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set_case_analysis 0 [get_ports in1]
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# Value 1
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set_case_analysis 1 [get_ports in2]
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# Value rising
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set_case_analysis rising [get_ports in3]
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# Write with case analysis
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set sdc4 [make_result_file sdc_cap_prop4.sdc]
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write_sdc -no_timestamp $sdc4
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# Unset case analysis
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unset_case_analysis [get_ports in1]
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unset_case_analysis [get_ports in2]
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unset_case_analysis [get_ports in3]
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# Value falling
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set_case_analysis falling [get_ports in1]
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# Write with falling
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set sdc5 [make_result_file sdc_cap_prop5.sdc]
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write_sdc -no_timestamp $sdc5
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# Unset
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unset_case_analysis [get_ports in1]
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# Test 9: Logic values
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set_logic_zero [get_ports in1]
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set_logic_one [get_ports in2]
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set_logic_dc [get_ports in3]
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set sdc6 [make_result_file sdc_cap_prop6.sdc]
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write_sdc -no_timestamp $sdc6
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