72 lines
2.3 KiB
Tcl
72 lines
2.3 KiB
Tcl
# Test 5: Write and re-read complex bus design with removes
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source ../../test/helpers.tcl
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suppress_msg 1140
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proc assert_file_nonempty {path} {
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if {![file exists $path]} {
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error "expected non-empty file: $path"
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}
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set in [open $path r]
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set text [read $in]
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close $in
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if {[string length $text] <= 0} {
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error "expected non-empty file: $path"
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}
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}
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proc assert_file_contains {path token} {
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set in [open $path r]
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set text [read $in]
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close $in
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if {[string first $token $text] < 0} {
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error "expected '$token' in $path"
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}
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}
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proc assert_file_not_contains {path token} {
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set in [open $path r]
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set text [read $in]
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close $in
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if {[string first $token $text] >= 0} {
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error "did not expect '$token' in $path"
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}
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}
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#---------------------------------------------------------------
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# Test 5: Write and re-read complex bus design with removes
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#---------------------------------------------------------------
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puts "--- Test 5: complex bus with removes ---"
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read_liberty ../../test/nangate45/Nangate45_typ.lib
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read_verilog verilog_complex_bus_test.v
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link_design verilog_complex_bus_test
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set out_cb_rm [make_result_file verilog_remove_complex_buf.v]
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write_verilog -remove_cells {BUF_X1} $out_cb_rm
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assert_file_nonempty $out_cb_rm
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assert_file_contains $out_cb_rm "module verilog_complex_bus_test"
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assert_file_not_contains $out_cb_rm " BUF_X1 "
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set out_cb_rm2 [make_result_file verilog_remove_complex_dff.v]
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write_verilog -remove_cells {DFF_X1} $out_cb_rm2
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assert_file_nonempty $out_cb_rm2
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assert_file_contains $out_cb_rm2 "module verilog_complex_bus_test"
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assert_file_not_contains $out_cb_rm2 " DFF_X1 "
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diff_files verilog_remove_complex_buf.vok $out_cb_rm
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diff_files verilog_remove_complex_dff.vok $out_cb_rm2
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read_liberty ../../test/nangate45/Nangate45_typ.lib
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read_verilog $out_cb_rm
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link_design verilog_complex_bus_test
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create_clock -name clk -period 10 [get_ports clk]
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set_input_delay -clock clk 0 [get_ports {data_a[*]}]
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set_input_delay -clock clk 0 [get_ports {data_b[*]}]
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set_output_delay -clock clk 0 [get_ports {result[*]}]
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set_output_delay -clock clk 0 [get_ports carry]
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set_output_delay -clock clk 0 [get_ports overflow]
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set_input_transition 0.1 [all_inputs]
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with_output_to_variable rm_rep { report_checks -path_delay max }
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if {![regexp {Path Type:\s+max} $rm_rep]} {
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error "remove_cells complex roundtrip timing report missing max path"
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}
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