147 lines
5.3 KiB
Tcl
147 lines
5.3 KiB
Tcl
# Test MakeTimingModel.cc: generate timing model, read it back, and run STA
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# on it. Exercises makeTimingModel with clock setup, findTimingFromInputs,
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# findClkedOutputPaths, findClkTreeDelays, makeGateModelScalar,
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# makeEndTimingArcs, saveSdc/restoreSdc, makeLibrary, makeCell, makePorts.
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# Also exercises model output with different designs (latch, CRPR).
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# Targets: MakeTimingModel.cc all major functions,
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# Sta.cc writeTimingModel
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source ../../test/helpers.tcl
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proc rename_timing_model_library {lib_file new_lib_name} {
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set in [open $lib_file r]
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set lib_text [read $in]
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close $in
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regsub {library[[:space:]]*\([^)]+\)} $lib_text "library ($new_lib_name)" lib_text
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set out [open $lib_file w]
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puts -nonewline $out $lib_text
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close $out
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}
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############################################################
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# Part 1: Model from search_path_end_types (flops with async reset)
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############################################################
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read_liberty ../../test/nangate45/Nangate45_typ.lib
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read_verilog search_path_end_types.v
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link_design search_path_end_types
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create_clock -name clk -period 10 [get_ports clk]
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set_input_delay -clock clk 1.0 [get_ports in1]
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set_input_delay -clock clk 1.0 [get_ports in2]
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set_input_delay -clock clk 0.5 [get_ports rst]
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set_output_delay -clock clk 2.0 [get_ports out1]
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set_output_delay -clock clk 2.0 [get_ports out2]
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set_output_delay -clock clk 2.0 [get_ports out3]
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set_input_transition 0.1 [all_inputs]
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report_checks -path_delay max > /dev/null
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puts "--- write_timing_model for search_path_end_types ---"
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set model1 [make_result_file "model_pet.lib"]
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write_timing_model -library_name model_pet_lib -cell_name model_pet $model1
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rename_timing_model_library $model1 model_pet_lib_readback
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# Read model back
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puts "--- read back model ---"
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read_liberty $model1
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############################################################
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# Part 2: Model from search_crpr (clock tree reconvergence)
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############################################################
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read_verilog search_crpr.v
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link_design search_crpr
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create_clock -name clk -period 10 [get_ports clk]
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set_propagated_clock [get_clocks clk]
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set_input_delay -clock clk 1.0 [get_ports in1]
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set_input_delay -clock clk 1.0 [get_ports in2]
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set_output_delay -clock clk 2.0 [get_ports out1]
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set_input_transition 0.1 [all_inputs]
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report_checks -path_delay max > /dev/null
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puts "--- write_timing_model for crpr design ---"
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set model2 [make_result_file "model_crpr.lib"]
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write_timing_model -library_name model_crpr_lib -cell_name model_crpr $model2
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rename_timing_model_library $model2 model_crpr_lib_readback
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puts "--- read back crpr model ---"
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read_liberty $model2
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############################################################
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# Part 3: Model from search_latch (latch design)
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############################################################
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read_verilog search_latch.v
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link_design search_latch
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create_clock -name clk -period 10 [get_ports clk]
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set_input_delay -clock clk 1.0 [get_ports in1]
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set_input_delay -clock clk 1.0 [get_ports in2]
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set_output_delay -clock clk 2.0 [get_ports out1]
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set_output_delay -clock clk 2.0 [get_ports out2]
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set_input_transition 0.1 [all_inputs]
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report_checks -path_delay max > /dev/null
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puts "--- write_timing_model for latch design ---"
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set model3 [make_result_file "model_latch.lib"]
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write_timing_model $model3
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rename_timing_model_library $model3 model_latch_readback
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puts "--- read back latch model ---"
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read_liberty $model3
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############################################################
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# Part 4: Model from search_test1 (simple flop design)
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############################################################
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read_verilog search_test1.v
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link_design search_test1
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create_clock -name clk -period 10 [get_ports clk]
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set_input_delay -clock clk 1.0 [get_ports in1]
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set_input_delay -clock clk 1.0 [get_ports in2]
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set_output_delay -clock clk 2.0 [get_ports out1]
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set_input_transition 0.1 [all_inputs]
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report_checks -path_delay max > /dev/null
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puts "--- write_timing_model default ---"
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set model4 [make_result_file "model_simple.lib"]
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write_timing_model $model4
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rename_timing_model_library $model4 model_simple_readback
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puts "--- write_timing_model with scene ---"
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set corner [sta::cmd_scene]
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set model5 [make_result_file "model_simple_corner.lib"]
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write_timing_model -scene $corner $model5
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rename_timing_model_library $model5 model_simple_corner_readback
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# Read model back and use it as a block
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puts "--- read back and use as block ---"
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read_liberty $model4
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############################################################
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# Part 5: write_timing_model on multicorner design
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############################################################
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read_verilog search_multicorner_analysis.v
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link_design search_multicorner_analysis
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create_clock -name clk -period 10 [get_ports clk]
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set_input_delay -clock clk 1.0 [get_ports in1]
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set_input_delay -clock clk 1.0 [get_ports in2]
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set_input_delay -clock clk 1.0 [get_ports in3]
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set_output_delay -clock clk 2.0 [get_ports out1]
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set_output_delay -clock clk 2.0 [get_ports out2]
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set_input_transition 0.1 [all_inputs]
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report_checks -path_delay max > /dev/null
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puts "--- write_timing_model for multicorner analysis ---"
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set model6 [make_result_file "model_multicorner.lib"]
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write_timing_model -library_name mc_lib -cell_name mc_cell $model6
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rename_timing_model_library $model6 model_multicorner_readback
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puts "--- read back multicorner model ---"
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read_liberty $model6
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