474 lines
14 KiB
Plaintext
474 lines
14 KiB
Plaintext
--- report_arrival on various pins ---
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(clk ^) r 1.04:1.05 f 1.05:1.05
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(clk ^) r 0.08:0.08 f 0.08:0.08
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(clk ^) r 0.00:0.00 f ---:---
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(clk v) r ---:--- f 5.00:5.00
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(clk ^) r 1.02:1.03 f 1.02:1.02
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(clk ^) r 1.04:1.05 f 1.05:1.05
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(clk ^) r 1.00:1.00 f 1.00:1.00
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(clk ^) r 0.10:0.10 f 0.10:0.10
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--- report_required on various pins ---
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(clk ^) r 0.00:9.97 f 0.00:9.96
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(clk ^) r -2.00:8.00 f -2.00:8.00
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--- report_slack on various pins ---
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(clk ^) r 1.04:8.92 f 1.04:8.91
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(clk ^) r 2.10:7.90 f 2.10:7.90
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--- worst_slack and TNS for each corner ---
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Worst slack max: 7.899713995438537
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Worst slack min: 1.0391781063125174
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TNS max: 0.0
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TNS min: 0.0
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WNS max: 0.0
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WNS min: 0.0
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--- report_checks with set_max_delay path ---
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No paths found.
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No paths found.
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No paths found.
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--- report_checks with set_min_delay path ---
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No paths found.
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No paths found.
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--- report_checks with set_false_path ---
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: out1 (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg1/CK (DFF_X1)
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0.08 0.08 ^ reg1/Q (DFF_X1)
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0.02 0.10 ^ buf2/Z (BUF_X1)
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0.00 0.10 ^ out1 (out)
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0.10 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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-2.00 8.00 output external delay
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8.00 data required time
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---------------------------------------------------------
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8.00 data required time
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-0.10 data arrival time
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---------------------------------------------------------
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7.90 slack (MET)
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--- report_checks with multicycle path ---
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Startpoint: in1 (input port clocked by clk)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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1.00 1.00 v input external delay
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0.00 1.00 v in1 (in)
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0.02 1.02 v and1/ZN (AND2_X1)
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0.02 1.05 v buf1/Z (BUF_X1)
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0.00 1.05 v reg1/D (DFF_X1)
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1.05 data arrival time
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30.00 30.00 clock clk (rise edge)
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0.00 30.00 clock network delay (ideal)
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0.00 30.00 clock reconvergence pessimism
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30.00 ^ reg1/CK (DFF_X1)
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-0.04 29.96 library setup time
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29.96 data required time
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---------------------------------------------------------
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29.96 data required time
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-1.05 data arrival time
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---------------------------------------------------------
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28.92 slack (MET)
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Startpoint: in1 (input port clocked by clk)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: min
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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1.00 1.00 ^ input external delay
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0.00 1.00 ^ in1 (in)
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0.02 1.02 ^ and1/ZN (AND2_X1)
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0.02 1.04 ^ buf1/Z (BUF_X1)
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0.00 1.04 ^ reg1/D (DFF_X1)
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1.04 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 ^ reg1/CK (DFF_X1)
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0.00 0.00 library hold time
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0.00 data required time
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---------------------------------------------------------
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0.00 data required time
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-1.04 data arrival time
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---------------------------------------------------------
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1.04 slack (MET)
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--- report_disabled_edges ---
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buf1 A Z constraint
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--- report_constant ---
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in2 1 case=1
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VDD X
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VSS X
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A1 X
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A2 1
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ZN X
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A2 1
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--- set_clock_uncertainty setup/hold ---
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: out1 (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg1/CK (DFF_X1)
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0.08 0.08 ^ reg1/Q (DFF_X1)
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0.02 0.10 ^ buf2/Z (BUF_X1)
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0.00 0.10 ^ out1 (out)
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0.10 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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-0.20 9.80 clock uncertainty
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0.00 9.80 clock reconvergence pessimism
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-2.00 7.80 output external delay
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7.80 data required time
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---------------------------------------------------------
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7.80 data required time
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-0.10 data arrival time
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---------------------------------------------------------
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7.70 slack (MET)
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Startpoint: in1 (input port clocked by clk)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: min
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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1.00 1.00 ^ input external delay
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0.00 1.00 ^ in1 (in)
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0.02 1.02 ^ and1/ZN (AND2_X1)
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0.02 1.04 ^ buf1/Z (BUF_X1)
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0.00 1.04 ^ reg1/D (DFF_X1)
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1.04 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.10 0.10 clock uncertainty
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0.00 0.10 clock reconvergence pessimism
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0.10 ^ reg1/CK (DFF_X1)
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0.00 0.10 library hold time
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0.10 data required time
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---------------------------------------------------------
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0.10 data required time
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-1.04 data arrival time
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---------------------------------------------------------
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0.94 slack (MET)
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--- set_clock_latency ---
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: out1 (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.55 0.55 clock network delay (ideal)
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0.00 0.55 ^ reg1/CK (DFF_X1)
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0.08 0.63 ^ reg1/Q (DFF_X1)
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0.02 0.65 ^ buf2/Z (BUF_X1)
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0.00 0.65 ^ out1 (out)
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0.65 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.40 10.40 clock network delay (ideal)
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0.00 10.40 clock reconvergence pessimism
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-2.00 8.40 output external delay
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8.40 data required time
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---------------------------------------------------------
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8.40 data required time
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-0.65 data arrival time
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---------------------------------------------------------
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7.75 slack (MET)
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Startpoint: in1 (input port clocked by clk)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: min
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.40 0.40 clock network delay (ideal)
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1.00 1.40 ^ input external delay
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0.00 1.40 ^ in1 (in)
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0.02 1.42 ^ and1/ZN (AND2_X1)
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0.02 1.44 ^ buf1/Z (BUF_X1)
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0.00 1.44 ^ reg1/D (DFF_X1)
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1.44 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.55 0.55 clock network delay (ideal)
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0.00 0.55 clock reconvergence pessimism
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0.55 ^ reg1/CK (DFF_X1)
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0.00 0.55 library hold time
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0.55 data required time
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---------------------------------------------------------
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0.55 data required time
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-1.44 data arrival time
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---------------------------------------------------------
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0.89 slack (MET)
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--- timing derate ---
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: out1 (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg1/CK (DFF_X1)
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0.09 0.09 ^ reg1/Q (DFF_X1)
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0.02 0.11 ^ buf2/Z (BUF_X1)
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0.00 0.11 ^ out1 (out)
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0.11 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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-2.00 8.00 output external delay
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8.00 data required time
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---------------------------------------------------------
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8.00 data required time
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-0.11 data arrival time
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---------------------------------------------------------
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7.89 slack (MET)
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Startpoint: in1 (input port clocked by clk)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: min
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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1.00 1.00 ^ input external delay
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0.00 1.00 ^ in1 (in)
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0.02 1.02 ^ and1/ZN (AND2_X1)
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0.02 1.04 ^ buf1/Z (BUF_X1)
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0.00 1.04 ^ reg1/D (DFF_X1)
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1.04 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 ^ reg1/CK (DFF_X1)
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0.00 0.00 library hold time
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0.00 data required time
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---------------------------------------------------------
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0.00 data required time
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-1.04 data arrival time
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---------------------------------------------------------
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1.04 slack (MET)
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--- report_checks -format json ---
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{"checks": [
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{
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"type": "output_delay",
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"path_group": "clk",
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"path_type": "max",
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"startpoint": "reg1/Q",
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"endpoint": "out1",
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"source_clock": "clk",
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"source_clock_edge": "rise",
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"source_clock_path": [
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{
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"instance": "",
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"cell": "search_test1",
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"verilog_src": "",
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"pin": "clk",
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"arrival": 0.000e+00,
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"capacitance": 9.497e-16,
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"slew": 0.000e+00
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},
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{
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"instance": "reg1",
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"cell": "DFF_X1",
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"verilog_src": "",
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"pin": "reg1/CK",
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"net": "clk",
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"arrival": 0.000e+00,
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"slew": 0.000e+00
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}
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],
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"source_path": [
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{
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"instance": "reg1",
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"cell": "DFF_X1",
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"verilog_src": "",
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"pin": "reg1/Q",
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"net": "n3",
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"arrival": 8.371e-11,
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"capacitance": 9.747e-16,
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"slew": 7.314e-12
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},
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{
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"instance": "buf2",
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"cell": "BUF_X1",
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"verilog_src": "",
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"pin": "buf2/A",
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"net": "n3",
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"arrival": 8.371e-11,
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"slew": 7.314e-12
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},
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{
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"instance": "buf2",
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"cell": "BUF_X1",
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"verilog_src": "",
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"pin": "buf2/Z",
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"net": "out1",
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"arrival": 1.003e-10,
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"capacitance": 0.000e+00,
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"slew": 3.638e-12
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},
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{
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"instance": "",
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"cell": "search_test1",
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"verilog_src": "",
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"pin": "out1",
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"arrival": 1.003e-10,
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"slew": 3.638e-12
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}
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],
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"target_clock": "clk",
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"target_clock_edge": "rise",
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"data_arrival_time": 1.003e-10,
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"crpr": 0.000e+00,
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"margin": 2.000e-09,
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"required_time": 8.000e-09,
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"slack": 7.900e-09
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}
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]
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}
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--- report_checks -format summary ---
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Startpoint Endpoint Slack
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--------------------------------------------------------------------------------
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reg1/Q (search_test1) out1 (output) 7.90
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Startpoint Endpoint Slack
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--------------------------------------------------------------------------------
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in1 (input) reg1/D (DFF_X1) 1.04
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--- report_checks -format slack_only ---
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Group Slack
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--------------------------------------------
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clk 7.90
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Group Slack
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--------------------------------------------
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clk 1.04
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--- report_checks -format end ---
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max_delay/setup group clk
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Required Actual
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Endpoint Delay Delay Slack
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------------------------------------------------------------
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out1 (output) 8.00 0.10 7.90 (MET)
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min_delay/hold group clk
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Required Actual
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Endpoint Delay Delay Slack
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------------------------------------------------------------
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reg1/D (DFF_X1) 0.00 1.04 1.04 (MET)
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min_delay/hold group clk
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Required Actual
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Endpoint Delay Delay Slack
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------------------------------------------------------------
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reg1/D (DFF_X1) 0.00 1.04 1.04 (MET)
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max_delay/setup group clk
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Required Actual
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Endpoint Delay Delay Slack
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------------------------------------------------------------
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out1 (output) 8.00 0.10 7.90 (MET)
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--- report_checks -format short ---
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: out1 (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Startpoint: in1 (input port clocked by clk)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: min
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--- pin_sim_logic_value ---
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sim logic value: X
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--- worst_clk_skew ---
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Worst clk skew setup: 0.0
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Worst clk skew hold: 0.0
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Worst clk skew setup (int): 0.0
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Worst clk skew hold (int): 0.0
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--- report_clock_skew with include_internal_latency ---
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Clock clk
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No launch/capture paths found.
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Clock clk
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No launch/capture paths found.
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--- report_clock_latency with include_internal_latency ---
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Clock clk
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rise -> rise
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min max
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0.00 0.00 source latency
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0.00 network latency reg1/CK
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0.00 network latency reg1/CK
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---------------
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0.00 0.00 latency
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0.00 skew
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fall -> fall
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min max
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0.00 0.00 source latency
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0.00 network latency reg1/CK
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0.00 network latency reg1/CK
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---------------
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0.00 0.00 latency
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0.00 skew
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