54 lines
2.1 KiB
Plaintext
54 lines
2.1 KiB
Plaintext
###############################################################################
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# Created by write_sdc
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###############################################################################
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current_design sdc_test2
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###############################################################################
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# Timing Constraints
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###############################################################################
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create_clock -name clk1 -period 10.0000 [get_ports {clk1}]
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create_clock -name clk2 -period 20.0000 [get_ports {clk2}]
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set_input_delay 2.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {in1}]
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set_input_delay 2.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {in2}]
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set_input_delay 2.0000 -clock [get_clocks {clk2}] -add_delay [get_ports {in3}]
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set_output_delay 3.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {out1}]
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set_output_delay 3.0000 -clock [get_clocks {clk2}] -add_delay [get_ports {out2}]
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set_false_path -setup\
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-from [get_clocks {clk1}]\
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-to [get_ports {out1}]
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set_false_path -setup\
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-from [get_ports {in3}]\
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-to [get_ports {out1}]
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set_false_path\
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-from [get_cells {reg1}]\
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-to [get_ports {out2}]
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set_false_path\
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-from [get_ports {in1}]\
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-to [get_cells {reg2}]
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set_false_path\
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-from [get_ports {in1}]\
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-through [get_cells {buf1}]\
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-to [get_ports {out2}]
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set_false_path\
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-from [get_ports {in1}]\
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-through [get_nets {n3}]\
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-through [get_pins {nand1/ZN}]\
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-to [get_ports {out1}]
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set_false_path\
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-from [get_ports {in2}]\
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-through [get_nets {n2}]\
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-to [get_ports {out1}]
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set_false_path\
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-from [list [get_ports {in1}]\
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[get_ports {in2}]]\
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-to [list [get_ports {out1}]\
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[get_ports {out2}]]
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set_false_path\
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-through [get_nets {n1}]\
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-to [get_ports {out1}]
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###############################################################################
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# Environment
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###############################################################################
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###############################################################################
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# Design Rules
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###############################################################################
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