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OpenSTA/verilog
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dsengupta0628 371b85cd20 latest STA plus changes to fix prima dcalc and read_spef issues, TCL regression added 
Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>
 		2026-04-07 20:48:15 +00:00
..
test Update golden files for upstream bias_pins feature 2026-04-02 12:42:08 +09:00
Verilog.i update copyright 2026-03-10 14:57:45 -07:00
Verilog.tcl update copyright 2026-03-10 14:57:45 -07:00
VerilogLex.ll string squash 2026-03-28 19:13:35 -07:00
VerilogParse.yy string squash 2026-03-28 19:13:35 -07:00
VerilogReader.cc string squash 2026-03-28 19:13:35 -07:00
VerilogReaderPvt.hh string squash 2026-03-28 19:13:35 -07:00
VerilogScanner.hh string squash 2026-03-28 19:13:35 -07:00
VerilogWriter.cc Bias pin handling (#409) 2026-04-07 11:00:01 -07:00