95 lines
2.8 KiB
Plaintext
95 lines
2.8 KiB
Plaintext
--- library queries ---
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total libraries: 4
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name: NangateOpenCellLibrary
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VDD supply exists: 1
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VSS supply exists: 1
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GND supply exists: 0
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NONEXISTENT: 0
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--- cross-library cell queries ---
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from library: NangateOpenCellLibrary
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from library: sky130_fd_sc_hd__tt_025C_1v80
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from library: sg13g2_stdcell_typ_1p20V_25C
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--- cell pattern matching ---
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Nangate INV*: 6
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Nangate BUF*: 6
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Nangate DFF*: 8
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Nangate SDFF*: 8
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Nangate all: 134
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Sky130 *inv*: 30
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Sky130 *buf*: 46
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Sky130 *dfxtp*: 10
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Sky130 *dlx*: 7
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Sky130 all: 428
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IHP all: 78
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--- cell port queries ---
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INV_X1 port match *: 4
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DFF_X1 port match *: 8
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SDFF_X1 port match *: 10
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FA_X1 port match *: 7
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CLKGATETST_X1 port match *: 7
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INV_X1 timing_arc_sets: 1
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DFF_X1 timing_arc_sets: 5
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SDFF_X1 timing_arc_sets: 9
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CLKGATETST_X1 timing_arc_sets: 9
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Startpoint: in1 (input port clocked by clk)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v in1 (in)
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0.04 0.04 v buf1/Z (BUF_X1)
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0.02 0.06 v and1/ZN (AND2_X1)
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0.00 0.06 v reg1/D (DFF_X1)
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0.06 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg1/CK (DFF_X1)
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-0.02 9.98 library setup time
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9.98 data required time
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---------------------------------------------------------
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9.98 data required time
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-0.06 data arrival time
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---------------------------------------------------------
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9.92 slack (MET)
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Startpoint: in1 (input port clocked by clk)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v in1 (in)
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0.04 0.04 v buf1/Z (BUF_X2)
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0.02 0.05 v and1/ZN (AND2_X1)
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0.00 0.05 v reg1/D (DFF_X1)
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0.05 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg1/CK (DFF_X1)
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-0.02 9.98 library setup time
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9.98 data required time
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---------------------------------------------------------
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9.98 data required time
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-0.05 data arrival time
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---------------------------------------------------------
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9.92 slack (MET)
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--- equiv cells multi-lib ---
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INV_X1 equivs: 6
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BUF_X1 equivs: 9
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