274 lines
7.8 KiB
Plaintext
274 lines
7.8 KiB
Plaintext
--- get_property on ports ---
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in1 direction: input
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out1 direction: output
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clk direction: input
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--- port direction queries ---
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input port count: 3
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output port count: 1
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--- get_property on instances ---
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buf1 ref_name: BUF_X1
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buf1 cell found: 1
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and1 ref_name: AND2_X1
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reg1 ref_name: DFF_X1
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--- get_property on pins ---
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buf1/A direction: input
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buf1/Z direction: output
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reg1/CK direction: input
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reg1/D direction: input
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reg1/Q direction: output
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--- get_property on nets ---
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n1 full_name: n1
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n2 full_name: n2
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--- get_cells with patterns ---
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cells with *: 3
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cells matching buf*: 1
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cells matching ref_name=~*X1: 3
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--- get_nets with patterns ---
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nets with *: 6
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nets matching n*: 2
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--- get_pins with patterns ---
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pins on buf1: 2
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pins matching */A: 1
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all hierarchical pins: 11
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--- find objects by name ---
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found buf1/Z: buf1/Z
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found n1: n1
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found buf1: buf1
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--- report_instance ---
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Instance buf1
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Cell: BUF_X1
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Library: NangateOpenCellLibrary
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Path cells: BUF_X1
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Input pins:
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A input in1
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Output pins:
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Z output n1
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Other pins:
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VDD power (unconnected)
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VSS ground (unconnected)
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Instance and1
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Cell: AND2_X1
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Library: NangateOpenCellLibrary
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Path cells: AND2_X1
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Input pins:
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A1 input n1
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A2 input in2
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Output pins:
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ZN output n2
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Other pins:
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VDD power (unconnected)
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VSS ground (unconnected)
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Instance reg1
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Cell: DFF_X1
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Library: NangateOpenCellLibrary
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Path cells: DFF_X1
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Input pins:
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D input n2
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CK input clk
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Output pins:
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Q output out1
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QN output (unconnected)
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Other pins:
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VDD power (unconnected)
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VSS ground (unconnected)
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IQ internal (unconnected)
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IQN internal (unconnected)
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--- report_net ---
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Net n1
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Pin capacitance: 0.87-0.92
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Wire capacitance: 0.00
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Total capacitance: 0.87-0.92
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Number of drivers: 1
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Number of loads: 1
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Number of pins: 2
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Driver pins
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buf1/Z output (BUF_X1)
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Load pins
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and1/A1 input (AND2_X1) 0.87-0.92
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Net n2
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Pin capacitance: 1.06-1.14
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Wire capacitance: 0.00
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Total capacitance: 1.06-1.14
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Number of drivers: 1
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Number of loads: 1
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Number of pins: 2
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Driver pins
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and1/ZN output (AND2_X1)
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Load pins
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reg1/D input (DFF_X1) 1.06-1.14
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--- hierarchical queries ---
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hierarchical cells: 3
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hierarchical nets: 6
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--- liberty cell queries ---
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found BUF_X1 lib cell: 1
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found AND2_X1 lib cell: 1
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found INV_X1 lib cell: 1
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--- sorting ---
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cell: and1
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cell: buf1
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cell: reg1
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net: clk
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net: in1
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net: in2
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net: n1
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net: n2
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net: out1
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pin: buf1/A
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pin: buf1/Z
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--- report_checks ---
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Startpoint: in1 (input port clocked by clk)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v in1 (in)
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0.02 0.02 v buf1/Z (BUF_X1)
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0.02 0.05 v and1/ZN (AND2_X1)
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0.00 0.05 v reg1/D (DFF_X1)
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0.05 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg1/CK (DFF_X1)
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-0.04 9.96 library setup time
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9.96 data required time
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---------------------------------------------------------
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9.96 data required time
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-0.05 data arrival time
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---------------------------------------------------------
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9.92 slack (MET)
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Startpoint: in2 (input port clocked by clk)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: min
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ input external delay
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0.00 0.00 ^ in2 (in)
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0.03 0.03 ^ and1/ZN (AND2_X1)
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0.00 0.03 ^ reg1/D (DFF_X1)
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0.03 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 ^ reg1/CK (DFF_X1)
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0.01 0.01 library hold time
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0.01 data required time
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---------------------------------------------------------
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0.01 data required time
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-0.03 data arrival time
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---------------------------------------------------------
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0.02 slack (MET)
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Startpoint: in1 (input port clocked by clk)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v in1 (in)
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0.02 0.02 v buf1/Z (BUF_X1)
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0.02 0.05 v and1/ZN (AND2_X1)
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0.00 0.05 v reg1/D (DFF_X1)
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0.05 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg1/CK (DFF_X1)
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-0.04 9.96 library setup time
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9.96 data required time
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---------------------------------------------------------
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9.96 data required time
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-0.05 data arrival time
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---------------------------------------------------------
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9.92 slack (MET)
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No paths found.
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No paths found.
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Warning 168: network_advanced.tcl line 1, unknown field nets.
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Startpoint: in1 (input port clocked by clk)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Fanout Cap Slew Delay Time Description
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-----------------------------------------------------------------------------
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0.00 0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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1 0.88 0.00 0.00 0.00 v in1 (in)
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0.00 0.00 0.00 v buf1/A (BUF_X1)
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1 0.87 0.00 0.02 0.02 v buf1/Z (BUF_X1)
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0.00 0.00 0.02 v and1/A1 (AND2_X1)
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1 1.06 0.01 0.02 0.05 v and1/ZN (AND2_X1)
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0.01 0.00 0.05 v reg1/D (DFF_X1)
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0.05 data arrival time
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0.00 10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg1/CK (DFF_X1)
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-0.04 9.96 library setup time
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9.96 data required time
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-----------------------------------------------------------------------------
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9.96 data required time
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-0.05 data arrival time
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-----------------------------------------------------------------------------
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9.92 slack (MET)
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Startpoint: in1 (input port clocked by clk)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v in1 (in)
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0.02 0.02 v buf1/Z (BUF_X1)
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0.02 0.05 v and1/ZN (AND2_X1)
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0.00 0.05 v reg1/D (DFF_X1)
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0.05 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg1/CK (DFF_X1)
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-0.04 9.96 library setup time
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9.96 data required time
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---------------------------------------------------------
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9.96 data required time
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-0.05 data arrival time
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---------------------------------------------------------
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9.92 slack (MET)
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