mirror of
https://github.com/The-OpenROAD-Project/OpenSTA.git
synced 2026-08-31 18:14:47 +02:00
Akash LevyandCursor
e9c075ab94
* Implement set_path_margin command Adds a new set_path_margin SDC command that applies a signed slack adjustment to the capture-clock side of timing paths. A positive margin tightens the path (harder to meet) and a negative margin loosens it. Supports -setup/-hold/-from/-through/-to scoping, priority/override semantics matching other exceptions, text and JSON report output, and write_sdc serialisation. Adapted from Silimate PR #57; uses upstream/master Mode/Scene and string_view APIs. Test uses unset_path_exceptions in place of the Silimate-only reset_path alias. Co-authored-by: Cursor <[email protected]> * Fix nested delaySum call indentation to match project style. Co-authored-by: Cursor <[email protected]> * Address review: store PathMargin on PathEnd, split tests Keep the path margin exception on PathEndClkConstrained, add PathEnd::hasPathMargin for report gating, and split the monolithic regression into set_path_margin1–6. Rebased onto upstream/master and document the command in ChangeLog. Co-authored-by: Cursor <[email protected]> * Document set_path_margin in OpenSTA.fodt/pdf Add the command reference, index entry, and note that unset_path_exceptions also clears path margin exceptions. Co-authored-by: Cursor <[email protected]> * Drop [[nodiscard]] from PathEnd::hasPathMargin. Co-authored-by: Cursor <[email protected]> --------- Co-authored-by: Cursor <[email protected]>
123 lines
4.4 KiB
Plaintext
123 lines
4.4 KiB
Plaintext
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
|
|
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
|
|
Path Group: clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
-------------------------------------------------------------
|
|
0.0000 0.0000 clock clk (rise edge)
|
|
0.0000 0.0000 clock network delay (ideal)
|
|
0.0000 0.0000 ^ r2/CK (DFF_X1)
|
|
0.0772 0.0772 v r2/Q (DFF_X1)
|
|
0.0233 0.1006 v u1/Z (BUF_X1)
|
|
0.0273 0.1278 v u2/ZN (AND2_X1)
|
|
0.0000 0.1278 v r3/D (DFF_X1)
|
|
0.1278 data arrival time
|
|
|
|
10.0000 10.0000 clock clk (rise edge)
|
|
0.0000 10.0000 clock network delay (ideal)
|
|
-0.5000 9.5000 path margin
|
|
0.0000 9.5000 clock reconvergence pessimism
|
|
9.5000 ^ r3/CK (DFF_X1)
|
|
-0.0390 9.4610 library setup time
|
|
9.4610 data required time
|
|
-------------------------------------------------------------
|
|
9.4610 data required time
|
|
-0.1278 data arrival time
|
|
-------------------------------------------------------------
|
|
9.3332 slack (MET)
|
|
|
|
|
|
setup_to_tighten -5.000e-10
|
|
Startpoint: r1 (rising edge-triggered flip-flop clocked by clk)
|
|
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
|
|
Path Group: clk
|
|
Path Type: min
|
|
|
|
Delay Time Description
|
|
-------------------------------------------------------------
|
|
0.0000 0.0000 clock clk (rise edge)
|
|
0.0000 0.0000 clock network delay (ideal)
|
|
0.0000 0.0000 ^ r1/CK (DFF_X1)
|
|
0.0772 0.0772 v r1/Q (DFF_X1)
|
|
0.0254 0.1026 v u2/ZN (AND2_X1)
|
|
0.0000 0.1026 v r3/D (DFF_X1)
|
|
0.1026 data arrival time
|
|
|
|
0.0000 0.0000 clock clk (rise edge)
|
|
0.0000 0.0000 clock network delay (ideal)
|
|
0.5000 0.5000 path margin
|
|
0.0000 0.5000 clock reconvergence pessimism
|
|
0.5000 ^ r3/CK (DFF_X1)
|
|
0.0016 0.5016 library hold time
|
|
0.5016 data required time
|
|
-------------------------------------------------------------
|
|
0.5016 data required time
|
|
-0.1026 data arrival time
|
|
-------------------------------------------------------------
|
|
-0.3990 slack (VIOLATED)
|
|
|
|
|
|
hold_to_tighten 5.000e-10
|
|
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
|
|
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
|
|
Path Group: clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
-------------------------------------------------------------
|
|
0.0000 0.0000 clock clk (rise edge)
|
|
0.0000 0.0000 clock network delay (ideal)
|
|
0.0000 0.0000 ^ r2/CK (DFF_X1)
|
|
0.0772 0.0772 v r2/Q (DFF_X1)
|
|
0.0233 0.1006 v u1/Z (BUF_X1)
|
|
0.0273 0.1278 v u2/ZN (AND2_X1)
|
|
0.0000 0.1278 v r3/D (DFF_X1)
|
|
0.1278 data arrival time
|
|
|
|
10.0000 10.0000 clock clk (rise edge)
|
|
0.0000 10.0000 clock network delay (ideal)
|
|
67.0000 77.0000 path margin
|
|
0.0000 77.0000 clock reconvergence pessimism
|
|
77.0000 ^ r3/CK (DFF_X1)
|
|
-0.0390 76.9610 library setup time
|
|
76.9610 data required time
|
|
-------------------------------------------------------------
|
|
76.9610 data required time
|
|
-0.1278 data arrival time
|
|
-------------------------------------------------------------
|
|
76.8332 slack (MET)
|
|
|
|
|
|
setup_to_loosen 6.700e-08
|
|
Startpoint: r1 (rising edge-triggered flip-flop clocked by clk)
|
|
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
|
|
Path Group: clk
|
|
Path Type: min
|
|
|
|
Delay Time Description
|
|
-------------------------------------------------------------
|
|
0.0000 0.0000 clock clk (rise edge)
|
|
0.0000 0.0000 clock network delay (ideal)
|
|
0.0000 0.0000 ^ r1/CK (DFF_X1)
|
|
0.0772 0.0772 v r1/Q (DFF_X1)
|
|
0.0254 0.1026 v u2/ZN (AND2_X1)
|
|
0.0000 0.1026 v r3/D (DFF_X1)
|
|
0.1026 data arrival time
|
|
|
|
0.0000 0.0000 clock clk (rise edge)
|
|
0.0000 0.0000 clock network delay (ideal)
|
|
-0.5000 -0.5000 path margin
|
|
0.0000 -0.5000 clock reconvergence pessimism
|
|
-0.5000 ^ r3/CK (DFF_X1)
|
|
0.0016 -0.4984 library hold time
|
|
-0.4984 data required time
|
|
-------------------------------------------------------------
|
|
-0.4984 data required time
|
|
-0.1026 data arrival time
|
|
-------------------------------------------------------------
|
|
0.6010 slack (MET)
|
|
|
|
|
|
hold_to_loosen -5.000e-10
|