257 lines
8.3 KiB
Tcl
257 lines
8.3 KiB
Tcl
# Test graph operations with larger multi-clock design for coverage.
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# Targets: Graph.cc (makeGraph, makeVerticesAndEdges, makeWireEdges,
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# makePinVertices, makeInstanceEdges, pinVertices, pinDrvrVertex,
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# pinLoadVertex, vertexCount, edgeCount, vertexIterator, edgeIterator,
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# arcDelayCount, hasDownstreamClkPin, regClkVertices, isRegClk,
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# isLatchData, widthCheckAnnotation, periodCheckAnnotation)
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# GraphCmp.cc (EdgeLess, sortEdges, VertexNameLess, vertexLess)
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source ../../test/helpers.tcl
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read_liberty ../../test/nangate45/Nangate45_typ.lib
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read_verilog graph_test3.v
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link_design graph_test3
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#---------------------------------------------------------------
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# Two clock domains
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#---------------------------------------------------------------
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create_clock -name clk1 -period 10 [get_ports clk1]
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create_clock -name clk2 -period 15 [get_ports clk2]
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set_input_delay -clock clk1 1.0 [get_ports {d1 d2 d3 d4}]
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set_output_delay -clock clk1 1.0 [get_ports {q1 q3}]
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set_output_delay -clock clk2 1.0 [get_ports q2]
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set_input_transition 0.1 [get_ports {d1 d2 d3 d4 rst clk1 clk2}]
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#---------------------------------------------------------------
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# Baseline timing (exercises makeGraph, graph construction)
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#---------------------------------------------------------------
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puts "--- baseline timing ---"
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report_checks
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report_checks -path_delay min
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report_checks -path_delay max
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#---------------------------------------------------------------
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# All path combinations (exercises vertex/edge traversal thoroughly)
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#---------------------------------------------------------------
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puts "--- all path combinations ---"
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foreach from_port {d1 d2 d3 d4} {
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foreach to_port {q1 q2 q3} {
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report_checks -from [get_ports $from_port] -to [get_ports $to_port]
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puts "${from_port}->${to_port}: done"
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}
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}
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#---------------------------------------------------------------
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# Through pin queries for reconvergent paths
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# Exercises: graph traversal through reconvergent fan-out
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#---------------------------------------------------------------
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puts "--- through reconvergent paths ---"
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report_checks -through [get_pins nand1/ZN]
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puts "through nand1/ZN: done"
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report_checks -through [get_pins nor1/ZN]
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puts "through nor1/ZN: done"
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report_checks -through [get_pins and2/ZN]
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puts "through and2/ZN: done"
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report_checks -through [get_pins or2/ZN]
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puts "through or2/ZN: done"
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# Through multiple intermediate points
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report_checks -through [get_pins and1/ZN] -through [get_pins nand1/ZN]
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puts "through and1->nand1: done"
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report_checks -through [get_pins or1/ZN] -through [get_pins nand1/ZN]
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puts "through or1->nand1: done"
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#---------------------------------------------------------------
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# Timing edge queries for all cells (exercises edge iteration)
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#---------------------------------------------------------------
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puts "--- timing edges all cells ---"
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foreach cell_name {buf1 buf2 inv1 inv2 and1 or1 nand1 nor1 and2 or2 reg1 reg2 reg3 buf3 buf4} {
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set edges [get_timing_edges -of_objects [get_cells $cell_name]]
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puts "$cell_name edges: [llength $edges]"
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}
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# From/to specific pins
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puts "--- specific edge queries ---"
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set edges_and1_a1 [get_timing_edges -from [get_pins and1/A1] -to [get_pins and1/ZN]]
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puts "and1 A1->ZN: [llength $edges_and1_a1]"
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set edges_and1_a2 [get_timing_edges -from [get_pins and1/A2] -to [get_pins and1/ZN]]
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puts "and1 A2->ZN: [llength $edges_and1_a2]"
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set edges_or1_a1 [get_timing_edges -from [get_pins or1/A1] -to [get_pins or1/ZN]]
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puts "or1 A1->ZN: [llength $edges_or1_a1]"
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set edges_nand_a1 [get_timing_edges -from [get_pins nand1/A1] -to [get_pins nand1/ZN]]
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puts "nand1 A1->ZN: [llength $edges_nand_a1]"
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set edges_nor_a1 [get_timing_edges -from [get_pins nor1/A1] -to [get_pins nor1/ZN]]
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puts "nor1 A1->ZN: [llength $edges_nor_a1]"
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# DFF edges
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set edges_reg1_ck_q [get_timing_edges -from [get_pins reg1/CK] -to [get_pins reg1/Q]]
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puts "reg1 CK->Q: [llength $edges_reg1_ck_q]"
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set edges_reg3_ck_q [get_timing_edges -from [get_pins reg3/CK] -to [get_pins reg3/Q]]
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puts "reg3 CK->Q: [llength $edges_reg3_ck_q]"
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#---------------------------------------------------------------
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# Report edges for all cell types
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#---------------------------------------------------------------
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puts "--- report_edges ---"
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report_edges -from [get_pins buf1/A] -to [get_pins buf1/Z]
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report_edges -from [get_pins inv1/A] -to [get_pins inv1/ZN]
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report_edges -from [get_pins and1/A1] -to [get_pins and1/ZN]
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report_edges -from [get_pins and1/A2] -to [get_pins and1/ZN]
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report_edges -from [get_pins or1/A1] -to [get_pins or1/ZN]
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report_edges -from [get_pins nand1/A1] -to [get_pins nand1/ZN]
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report_edges -from [get_pins nor1/A1] -to [get_pins nor1/ZN]
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report_edges -from [get_pins reg1/CK] -to [get_pins reg1/Q]
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report_edges -from [get_pins reg3/CK] -to [get_pins reg3/Q]
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# From only
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report_edges -from [get_ports d1]
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report_edges -from [get_ports d3]
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# To only
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report_edges -to [get_ports q1]
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report_edges -to [get_ports q2]
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report_edges -to [get_ports q3]
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#---------------------------------------------------------------
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# Disable/enable timing on various cells
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# Exercises: graph edge disable/enable, re-traversal
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#---------------------------------------------------------------
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puts "--- disable/enable timing ---"
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# Disable individual cells
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set_disable_timing [get_cells buf1]
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report_checks
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set_disable_timing [get_cells inv1]
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report_checks
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set_disable_timing [get_cells nand1]
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report_checks
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# Enable back one by one
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unset_disable_timing [get_cells buf1]
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report_checks
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unset_disable_timing [get_cells inv1]
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report_checks
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unset_disable_timing [get_cells nand1]
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report_checks
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# Disable specific arcs on lib cells
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set_disable_timing -from A1 -to ZN [get_lib_cells NangateOpenCellLibrary/AND2_X1]
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report_disabled_edges
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report_checks
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unset_disable_timing -from A1 -to ZN [get_lib_cells NangateOpenCellLibrary/AND2_X1]
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report_disabled_edges
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report_checks
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# Disable/enable on NOR and NAND
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set_disable_timing -from A1 -to ZN [get_lib_cells NangateOpenCellLibrary/NAND2_X1]
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report_checks
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unset_disable_timing -from A1 -to ZN [get_lib_cells NangateOpenCellLibrary/NAND2_X1]
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report_checks
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set_disable_timing -from A1 -to ZN [get_lib_cells NangateOpenCellLibrary/NOR2_X1]
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report_checks
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unset_disable_timing -from A1 -to ZN [get_lib_cells NangateOpenCellLibrary/NOR2_X1]
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report_checks
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#---------------------------------------------------------------
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# Case analysis / constant propagation
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# Exercises: graph constant propagation, re-traversal
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#---------------------------------------------------------------
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puts "--- case analysis ---"
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set_case_analysis 1 [get_ports rst]
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report_checks
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set_case_analysis 0 [get_ports rst]
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report_checks
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unset_case_analysis [get_ports rst]
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report_checks
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# Case analysis on data inputs
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set_case_analysis 1 [get_ports d3]
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report_checks
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unset_case_analysis [get_ports d3]
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report_checks
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#---------------------------------------------------------------
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# Report slews for pins in multi-clock design
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# Exercises: vertex slew access across corners
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#---------------------------------------------------------------
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puts "--- report_slews ---"
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report_slews [get_ports d1]
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report_slews [get_ports d2]
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report_slews [get_ports d3]
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report_slews [get_ports d4]
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report_slews [get_ports q1]
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report_slews [get_ports q2]
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report_slews [get_ports q3]
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report_slews [get_pins buf1/Z]
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report_slews [get_pins inv1/ZN]
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report_slews [get_pins and1/ZN]
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report_slews [get_pins or1/ZN]
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report_slews [get_pins nand1/ZN]
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report_slews [get_pins nor1/ZN]
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report_slews [get_pins and2/ZN]
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report_slews [get_pins or2/ZN]
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report_slews [get_pins reg1/Q]
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report_slews [get_pins reg2/Q]
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report_slews [get_pins reg3/Q]
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#---------------------------------------------------------------
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# report_check_types (exercises check edge categorization)
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#---------------------------------------------------------------
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puts "--- report_check_types ---"
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report_check_types -max_delay -verbose
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report_check_types -min_delay -verbose
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report_check_types -max_delay -min_delay -verbose
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#---------------------------------------------------------------
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# report_checks with various options
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#---------------------------------------------------------------
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puts "--- report_checks options ---"
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report_checks -fields {slew cap input_pins nets fanout}
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report_checks -format full_clock
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report_checks -unconstrained
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report_checks -group_count 3
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report_checks -endpoint_count 5
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report_checks -sort_by_slack
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report_checks -endpoint_count 3 -path_delay min
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