OpenSTA/liberty/test/liberty_properties.ok

Cell INV_X1
Library NangateOpenCellLibrary
File ../../test/nangate45/Nangate45_typ.lib
 VDD power
 VSS ground
 A input 1.55-1.70
 ZN output function=!A

Timing arcs
 A -> ZN
  combinational
  ^ -> v
  v -> ^
Cell BUF_X1
Library NangateOpenCellLibrary
File ../../test/nangate45/Nangate45_typ.lib
 VDD power
 VSS ground
 A input 0.88-0.97
 Z output function=A

Timing arcs
 A -> Z
  combinational
  ^ -> ^
  v -> v
Cell DFF_X1
Library NangateOpenCellLibrary
File ../../test/nangate45/Nangate45_typ.lib
 VDD power
 VSS ground
 D input 1.06-1.14
 CK input 0.86-0.95
 Q output function=IQ
 QN output function=IQN
 IQ internal
 IQN internal

Timing arcs
 CK -> D
  hold
  ^ -> ^
  ^ -> v
 CK -> D
  setup
  ^ -> ^
  ^ -> v
 CK -> CK
  width
  ^ -> v
  v -> ^
 CK -> Q
  Reg Clk to Q
  ^ -> ^
  ^ -> v
 CK -> QN
  Reg Clk to Q
  ^ -> ^
  ^ -> v
Cell DFFR_X1
Library NangateOpenCellLibrary
File ../../test/nangate45/Nangate45_typ.lib
 VDD power
 VSS ground
 D input 1.05-1.13
 RN input 1.74-1.78
 CK input 0.88-0.98
 Q output function=IQ
 QN output function=IQN
 IQ internal
 IQN internal

Timing arcs
 CK -> D
  hold
  when RN
  ^ -> ^
  ^ -> v
 CK -> D
  setup
  when RN
  ^ -> ^
  ^ -> v
 CK -> RN
  recovery
  ^ -> ^
 CK -> RN
  removal
  ^ -> ^
 RN -> RN
  width
  v -> ^
 CK -> CK
  width
  when RN
  ^ -> v
  v -> ^
 CK -> Q
  Reg Clk to Q
  ^ -> ^
  ^ -> v
 RN -> Q
  Reg Set/Clr
  when !CK*!D
  v -> v
 RN -> Q
  Reg Set/Clr
  when !CK*D
  v -> v
 RN -> Q
  Reg Set/Clr
  when CK*!D
  v -> v
 RN -> Q
  Reg Set/Clr
  when CK*D
  v -> v
 CK -> QN
  Reg Clk to Q
  ^ -> ^
  ^ -> v
 RN -> QN
  Reg Set/Clr
  when !CK*!D
  v -> ^
 RN -> QN
  Reg Set/Clr
  when !CK*D
  v -> ^
 RN -> QN
  Reg Set/Clr
  when CK*!D
  v -> ^
 RN -> QN
  Reg Set/Clr
  when CK*D
  v -> ^
Cell DFFS_X1
Library NangateOpenCellLibrary
File ../../test/nangate45/Nangate45_typ.lib
 VDD power
 VSS ground
 D input 1.09-1.16
 SN input 1.33-1.36
 CK input 0.88-0.97
 Q output function=IQ
 QN output function=IQN
 IQ internal
 IQN internal

Timing arcs
 CK -> D
  hold
  when SN
  ^ -> ^
  ^ -> v
 CK -> D
  setup
  when SN
  ^ -> ^
  ^ -> v
 CK -> SN
  recovery
  ^ -> ^
 CK -> SN
  removal
  ^ -> ^
 SN -> SN
  width
  v -> ^
 CK -> CK
  width
  when SN
  ^ -> v
  v -> ^
 CK -> Q
  Reg Clk to Q
  ^ -> ^
  ^ -> v
 SN -> Q
  Reg Set/Clr
  when !CK*!D
  v -> ^
 SN -> Q
  Reg Set/Clr
  when !CK*D
  v -> ^
 SN -> Q
  Reg Set/Clr
  when CK*!D
  v -> ^
 SN -> Q
  Reg Set/Clr
  when CK*D
  v -> ^
 CK -> QN
  Reg Clk to Q
  ^ -> ^
  ^ -> v
 SN -> QN
  Reg Set/Clr
  when !CK*!D
  v -> v
 SN -> QN
  Reg Set/Clr
  when !CK*D
  v -> v
 SN -> QN
  Reg Set/Clr
  when CK*!D
  v -> v
 SN -> QN
  Reg Set/Clr
  when CK*D
  v -> v
Cell DFFRS_X1
Library NangateOpenCellLibrary
File ../../test/nangate45/Nangate45_typ.lib
 VDD power
 VSS ground
 D input 1.08-1.15
 RN input 1.38-1.41
 SN input 2.10-2.21
 CK input 0.87-0.96
 Q output function=IQ
 QN output function=IQN
 IQ internal
 IQN internal

Timing arcs
 CK -> D
  hold
  when RN*SN
  ^ -> ^
  ^ -> v
 CK -> D
  setup
  when RN*SN
  ^ -> ^
  ^ -> v
 CK -> RN
  recovery
  when SN
  ^ -> ^
 CK -> RN
  removal
  when SN
  ^ -> ^
 RN -> RN
  width
  when SN
  v -> ^
 CK -> SN
  recovery
  when RN
  ^ -> ^
 CK -> SN
  removal
  when RN
  ^ -> ^
 SN -> SN
  width
  when RN
  v -> ^
 CK -> CK
  width
  when RN*SN
  ^ -> v
  v -> ^
 CK -> Q
  Reg Clk to Q
  ^ -> ^
  ^ -> v
 RN -> Q
  Reg Set/Clr
  when (!CK*!D)*!SN
  v -> v
 RN -> Q
  Reg Set/Clr
  when (!CK*!D)*SN
  v -> v
 RN -> Q
  Reg Set/Clr
  when (!CK*D)*!SN
  v -> v
 RN -> Q
  Reg Set/Clr
  when (!CK*D)*SN
  v -> v
 RN -> Q
  Reg Set/Clr
  when (CK*!D)*!SN
  v -> v
 RN -> Q
  Reg Set/Clr
  when (CK*!D)*SN
  v -> v
 RN -> Q
  Reg Set/Clr
  when (CK*D)*!SN
  v -> v
 RN -> Q
  Reg Set/Clr
  when (CK*D)*SN
  v -> v
 SN -> Q
  Reg Set/Clr
  when (!CK*!D)*RN
  v -> ^
 SN -> Q
  Reg Set/Clr
  when (!CK*D)*RN
  v -> ^
 SN -> Q
  Reg Set/Clr
  when (CK*!D)*RN
  v -> ^
 SN -> Q
  Reg Set/Clr
  when (CK*D)*RN
  v -> ^
 CK -> QN
  Reg Clk to Q
  ^ -> ^
  ^ -> v
 RN -> QN
  Reg Set/Clr
  when (!CK*!D)*SN
  v -> ^
 RN -> QN
  Reg Set/Clr
  when (!CK*D)*SN
  v -> ^
 RN -> QN
  Reg Set/Clr
  when (CK*!D)*SN
  v -> ^
 RN -> QN
  Reg Set/Clr
  when (CK*D)*SN
  v -> ^
 SN -> QN
  Reg Set/Clr
  when (!CK*!D)*!RN
  v -> v
 SN -> QN
  Reg Set/Clr
  when (!CK*!D)*RN
  v -> v
 SN -> QN
  Reg Set/Clr
  when (!CK*D)*!RN
  v -> v
 SN -> QN
  Reg Set/Clr
  when (!CK*D)*RN
  v -> v
 SN -> QN
  Reg Set/Clr
  when (CK*!D)*!RN
  v -> v
 SN -> QN
  Reg Set/Clr
  when (CK*!D)*RN
  v -> v
 SN -> QN
  Reg Set/Clr
  when (CK*D)*!RN
  v -> v
 SN -> QN
  Reg Set/Clr
  when (CK*D)*RN
  v -> v
Cell TLAT_X1
Library NangateOpenCellLibrary
File ../../test/nangate45/Nangate45_typ.lib
 VDD power
 VSS ground
 D input 1.07-1.14
 G input 0.92-1.02
 OE input 1.42-1.50
 Q tristate enable=OE function=IQ 0.79-0.79
 IQ internal
 IQN internal

Timing arcs
 G -> D
  hold
  v -> ^
  v -> v
 G -> D
  setup
  v -> ^
  v -> v
 G -> G
  width
  ^ -> v
 D -> Q
  Latch D to Q
  ^ -> ^
  v -> v
 G -> Q
  Latch En to Q
  ^ -> ^
  ^ -> v
 OE -> Q
  tristate disable
  v -> 0Z
  v -> 1Z
 OE -> Q
  tristate enable
  ^ -> Z1
  ^ -> Z0
Cell AOI21_X1
Library NangateOpenCellLibrary
File ../../test/nangate45/Nangate45_typ.lib
 VDD power
 VSS ground
 A input 1.54-1.63
 B1 input 1.45-1.65
 B2 input 1.41-1.68
 ZN output function=!(A+(B1*B2))

Timing arcs
 A -> ZN
  combinational
  when !B1*!B2
  ^ -> v
  v -> ^
 A -> ZN
  combinational
  when !B1*B2
  ^ -> v
  v -> ^
 A -> ZN
  combinational
  when B1*!B2
  ^ -> v
  v -> ^
 B1 -> ZN
  combinational
  ^ -> v
  v -> ^
 B2 -> ZN
  combinational
  ^ -> v
  v -> ^
Cell AOI22_X1
Library NangateOpenCellLibrary
File ../../test/nangate45/Nangate45_typ.lib
 VDD power
 VSS ground
 A1 input 1.50-1.69
 A2 input 1.43-1.69
 B1 input 1.55-1.58
 B2 input 1.52-1.62
 ZN output function=!((A1*A2)+(B1*B2))

Timing arcs
 A1 -> ZN
  combinational
  when (A2*!B1)*!B2
  ^ -> v
  v -> ^
 A1 -> ZN
  combinational
  when (A2*!B1)*B2
  ^ -> v
  v -> ^
 A1 -> ZN
  combinational
  when (A2*B1)*!B2
  ^ -> v
  v -> ^
 A2 -> ZN
  combinational
  when (A1*!B1)*!B2
  ^ -> v
  v -> ^
 A2 -> ZN
  combinational
  when (A1*!B1)*B2
  ^ -> v
  v -> ^
 A2 -> ZN
  combinational
  when (A1*B1)*!B2
  ^ -> v
  v -> ^
 B1 -> ZN
  combinational
  when (!A1*!A2)*B2
  ^ -> v
  v -> ^
 B1 -> ZN
  combinational
  when (!A1*A2)*B2
  ^ -> v
  v -> ^
 B1 -> ZN
  combinational
  when (A1*!A2)*B2
  ^ -> v
  v -> ^
 B2 -> ZN
  combinational
  when (!A1*!A2)*B1
  ^ -> v
  v -> ^
 B2 -> ZN
  combinational
  when (!A1*A2)*B1
  ^ -> v
  v -> ^
 B2 -> ZN
  combinational
  when (A1*!A2)*B1
  ^ -> v
  v -> ^
Cell OAI21_X1
Library NangateOpenCellLibrary
File ../../test/nangate45/Nangate45_typ.lib
 VDD power
 VSS ground
 A input 1.52-1.67
 B1 input 1.46-1.66
 B2 input 1.56-1.57
 ZN output function=!(A*(B1+B2))

Timing arcs
 A -> ZN
  combinational
  when !B1*B2
  ^ -> v
  v -> ^
 A -> ZN
  combinational
  when B1*!B2
  ^ -> v
  v -> ^
 A -> ZN
  combinational
  when B1*B2
  ^ -> v
  v -> ^
 B1 -> ZN
  combinational
  ^ -> v
  v -> ^
 B2 -> ZN
  combinational
  ^ -> v
  v -> ^
Cell OAI22_X1
Library NangateOpenCellLibrary
File ../../test/nangate45/Nangate45_typ.lib
 VDD power
 VSS ground
 A1 input 1.46-1.67
 A2 input 1.56-1.58
 B1 input 1.41-1.67
 B2 input 1.55-1.62
 ZN output function=!((A1+A2)*(B1+B2))

Timing arcs
 A1 -> ZN
  combinational
  when (!A2*!B1)*B2
  ^ -> v
  v -> ^
 A1 -> ZN
  combinational
  when (!A2*B1)*!B2
  ^ -> v
  v -> ^
 A1 -> ZN
  combinational
  when (!A2*B1)*B2
  ^ -> v
  v -> ^
 A2 -> ZN
  combinational
  when (!A1*!B1)*B2
  ^ -> v
  v -> ^
 A2 -> ZN
  combinational
  when (!A1*B1)*!B2
  ^ -> v
  v -> ^
 A2 -> ZN
  combinational
  when (!A1*B1)*B2
  ^ -> v
  v -> ^
 B1 -> ZN
  combinational
  when (!A1*A2)*!B2
  ^ -> v
  v -> ^
 B1 -> ZN
  combinational
  when (A1*!A2)*!B2
  ^ -> v
  v -> ^
 B1 -> ZN
  combinational
  when (A1*A2)*!B2
  ^ -> v
  v -> ^
 B2 -> ZN
  combinational
  when (!A1*A2)*!B1
  ^ -> v
  v -> ^
 B2 -> ZN
  combinational
  when (A1*!A2)*!B1
  ^ -> v
  v -> ^
 B2 -> ZN
  combinational
  when (A1*A2)*!B1
  ^ -> v
  v -> ^
Cell AOI211_X1
Library NangateOpenCellLibrary
File ../../test/nangate45/Nangate45_typ.lib
 VDD power
 VSS ground
 A input 1.56-1.62
 B input 1.47-1.66
 C1 input 1.40-1.66
 C2 input 1.37-1.68
 ZN output function=!(((C1*C2)+B)+A)

Timing arcs
 A -> ZN
  combinational
  when (!B*!C1)*!C2
  ^ -> v
  v -> ^
 A -> ZN
  combinational
  when (!B*!C1)*C2
  ^ -> v
  v -> ^
 A -> ZN
  combinational
  when (!B*C1)*!C2
  ^ -> v
  v -> ^
 B -> ZN
  combinational
  when (!A*!C1)*!C2
  ^ -> v
  v -> ^
 B -> ZN
  combinational
  when (!A*!C1)*C2
  ^ -> v
  v -> ^
 B -> ZN
  combinational
  when (!A*C1)*!C2
  ^ -> v
  v -> ^
 C1 -> ZN
  combinational
  ^ -> v
  v -> ^
 C2 -> ZN
  combinational
  ^ -> v
  v -> ^
Cell OAI211_X1
Library NangateOpenCellLibrary
File ../../test/nangate45/Nangate45_typ.lib
 VDD power
 VSS ground
 A input 1.53-1.61
 B input 1.50-1.66
 C1 input 1.44-1.60
 C2 input 1.52-1.56
 ZN output function=!(((C1+C2)*A)*B)

Timing arcs
 A -> ZN
  combinational
  when (B*!C1)*C2
  ^ -> v
  v -> ^
 A -> ZN
  combinational
  when (B*C1)*!C2
  ^ -> v
  v -> ^
 A -> ZN
  combinational
  when (B*C1)*C2
  ^ -> v
  v -> ^
 B -> ZN
  combinational
  when (A*!C1)*C2
  ^ -> v
  v -> ^
 B -> ZN
  combinational
  when (A*C1)*!C2
  ^ -> v
  v -> ^
 B -> ZN
  combinational
  when (A*C1)*C2
  ^ -> v
  v -> ^
 C1 -> ZN
  combinational
  ^ -> v
  v -> ^
 C2 -> ZN
  combinational
  ^ -> v
  v -> ^
Cell HA_X1
Library NangateOpenCellLibrary
File ../../test/nangate45/Nangate45_typ.lib
 VDD power
 VSS ground
 A input 3.06-3.19
 B input 3.34-3.45
 CO output function=A*B
 S output function=A^B

Timing arcs
 A -> CO
  combinational
  ^ -> ^
  v -> v
 B -> CO
  combinational
  ^ -> ^
  v -> v
 A -> S
  combinational
  when !B
  ^ -> ^
  v -> v
 A -> S
  combinational
  when B
  ^ -> v
  v -> ^
 B -> S
  combinational
  when !A
  ^ -> ^
  v -> v
 B -> S
  combinational
  when A
  ^ -> v
  v -> ^
Cell FA_X1
Library NangateOpenCellLibrary
File ../../test/nangate45/Nangate45_typ.lib
 VDD power
 VSS ground
 A input 3.61-3.75
 B input 3.40-3.47
 CI input 2.66-2.76
 CO output function=(A*B)+(CI*(A+B))
 S output function=CI^(A^B)

Timing arcs
 A -> CO
  combinational
  when !B*CI
  ^ -> ^
  v -> v
 A -> CO
  combinational
  when B*!CI
  ^ -> ^
  v -> v
 B -> CO
  combinational
  when !A*CI
  ^ -> ^
  v -> v
 B -> CO
  combinational
  when A*!CI
  ^ -> ^
  v -> v
 CI -> CO
  combinational
  when !A*B
  ^ -> ^
  v -> v
 CI -> CO
  combinational
  when A*!B
  ^ -> ^
  v -> v
 A -> S
  combinational
  when !B*!CI
  ^ -> ^
  v -> v
 A -> S
  combinational
  when !B*CI
  ^ -> v
  v -> ^
 A -> S
  combinational
  when B*!CI
  ^ -> v
  v -> ^
 A -> S
  combinational
  when B*CI
  ^ -> ^
  v -> v
 B -> S
  combinational
  when !A*!CI
  ^ -> ^
  v -> v
 B -> S
  combinational
  when !A*CI
  ^ -> v
  v -> ^
 B -> S
  combinational
  when A*!CI
  ^ -> v
  v -> ^
 B -> S
  combinational
  when A*CI
  ^ -> ^
  v -> v
 CI -> S
  combinational
  when !A*!B
  ^ -> ^
  v -> v
 CI -> S
  combinational
  when !A*B
  ^ -> v
  v -> ^
 CI -> S
  combinational
  when A*!B
  ^ -> v
  v -> ^
 CI -> S
  combinational
  when A*B
  ^ -> ^
  v -> v
Cell XNOR2_X1
Library NangateOpenCellLibrary
File ../../test/nangate45/Nangate45_typ.lib
 VDD power
 VSS ground
 A input 2.13-2.23
 B input 2.37-2.57
 ZN output function=!(A^B)

Timing arcs
 A -> ZN
  combinational
  when !B
  ^ -> v
  v -> ^
 A -> ZN
  combinational
  when B
  ^ -> ^
  v -> v
 B -> ZN
  combinational
  when !A
  ^ -> v
  v -> ^
 B -> ZN
  combinational
  when A
  ^ -> ^
  v -> v
Cell XOR2_X1
Library NangateOpenCellLibrary
File ../../test/nangate45/Nangate45_typ.lib
 VDD power
 VSS ground
 A input 2.18-2.23
 B input 2.36-2.41
 Z output function=A^B

Timing arcs
 A -> Z
  combinational
  when !B
  ^ -> ^
  v -> v
 A -> Z
  combinational
  when B
  ^ -> v
  v -> ^
 B -> Z
  combinational
  when !A
  ^ -> ^
  v -> v
 B -> Z
  combinational
  when A
  ^ -> v
  v -> ^
Cell MUX2_X1
Library NangateOpenCellLibrary
File ../../test/nangate45/Nangate45_typ.lib
 VDD power
 VSS ground
 A input 0.91-0.95
 B input 0.90-0.94
 S input 1.81-1.92
 Z output function=(S*B)+(A*!S)

Timing arcs
 A -> Z
  combinational
  when !B*!S
  ^ -> ^
  v -> v
 A -> Z
  combinational
  when B*!S
  ^ -> ^
  v -> v
 B -> Z
  combinational
  when !A*S
  ^ -> ^
  v -> v
 B -> Z
  combinational
  when A*S
  ^ -> ^
  v -> v
 S -> Z
  combinational
  when !A*B
  ^ -> ^
  v -> v
 S -> Z
  combinational
  when A*!B
  ^ -> v
  v -> ^
Cell CLKBUF_X1
Library NangateOpenCellLibrary
File ../../test/nangate45/Nangate45_typ.lib
 VDD power
 VSS ground
 A input 0.70-0.78
 Z output function=A

Timing arcs
 A -> Z
  combinational
  ^ -> ^
  v -> v
Cell CLKBUF_X2
Library NangateOpenCellLibrary
File ../../test/nangate45/Nangate45_typ.lib
 VDD power
 VSS ground
 A input 1.24-1.41
 Z output function=A

Timing arcs
 A -> Z
  combinational
  ^ -> ^
  v -> v
Cell CLKBUF_X3
Library NangateOpenCellLibrary
File ../../test/nangate45/Nangate45_typ.lib
 VDD power
 VSS ground
 A input 1.25-1.42
 Z output function=A

Timing arcs
 A -> Z
  combinational
  ^ -> ^
  v -> v
Cell TINV_X1
Library NangateOpenCellLibrary
File ../../test/nangate45/Nangate45_typ.lib
 VDD power
 VSS ground
 EN input 1.64-1.75
 I input 1.38-1.44
 ZN tristate enable=!EN function=!I 0.80-0.80

Timing arcs
 EN -> ZN
  tristate disable
  ^ -> 0Z
  ^ -> 1Z
 EN -> ZN
  tristate enable
  v -> Z1
  v -> Z0
 I -> ZN
  combinational
  ^ -> v
  v -> ^
Cell NAND2_X1
Library NangateOpenCellLibrary
File ../../test/nangate45/Nangate45_typ.lib
 VDD power
 VSS ground
 A1 input 1.53-1.60
 A2 input 1.50-1.66
 ZN output function=!(A1*A2)

Timing arcs
 A1 -> ZN
  combinational
  ^ -> v
  v -> ^
 A2 -> ZN
  combinational
  ^ -> v
  v -> ^
Cell NAND3_X1
Library NangateOpenCellLibrary
File ../../test/nangate45/Nangate45_typ.lib
 VDD power
 VSS ground
 A1 input 1.56-1.59
 A2 input 1.53-1.62
 A3 input 1.49-1.65
 ZN output function=!((A1*A2)*A3)

Timing arcs
 A1 -> ZN
  combinational
  ^ -> v
  v -> ^
 A2 -> ZN
  combinational
  ^ -> v
  v -> ^
 A3 -> ZN
  combinational
  ^ -> v
  v -> ^
Cell NAND4_X1
Library NangateOpenCellLibrary
File ../../test/nangate45/Nangate45_typ.lib
 VDD power
 VSS ground
 A1 input 1.52-1.52
 A2 input 1.54-1.60
 A3 input 1.54-1.64
 A4 input 1.49-1.66
 ZN output function=!(((A1*A2)*A3)*A4)

Timing arcs
 A1 -> ZN
  combinational
  ^ -> v
  v -> ^
 A2 -> ZN
  combinational
  ^ -> v
  v -> ^
 A3 -> ZN
  combinational
  ^ -> v
  v -> ^
 A4 -> ZN
  combinational
  ^ -> v
  v -> ^
Cell NOR2_X1
Library NangateOpenCellLibrary
File ../../test/nangate45/Nangate45_typ.lib
 VDD power
 VSS ground
 A1 input 1.41-1.71
 A2 input 1.56-1.65
 ZN output function=!(A1+A2)

Timing arcs
 A1 -> ZN
  combinational
  ^ -> v
  v -> ^
 A2 -> ZN
  combinational
  ^ -> v
  v -> ^
Cell NOR3_X1
Library NangateOpenCellLibrary
File ../../test/nangate45/Nangate45_typ.lib
 VDD power
 VSS ground
 A1 input 1.40-1.76
 A2 input 1.48-1.66
 A3 input 1.55-1.62
 ZN output function=!((A1+A2)+A3)

Timing arcs
 A1 -> ZN
  combinational
  ^ -> v
  v -> ^
 A2 -> ZN
  combinational
  ^ -> v
  v -> ^
 A3 -> ZN
  combinational
  ^ -> v
  v -> ^
Cell NOR4_X1
Library NangateOpenCellLibrary
File ../../test/nangate45/Nangate45_typ.lib
 VDD power
 VSS ground
 A1 input 1.34-1.74
 A2 input 1.45-1.67
 A3 input 1.49-1.64
 A4 input 1.55-1.61
 ZN output function=!(((A1+A2)+A3)+A4)

Timing arcs
 A1 -> ZN
  combinational
  ^ -> v
  v -> ^
 A2 -> ZN
  combinational
  ^ -> v
  v -> ^
 A3 -> ZN
  combinational
  ^ -> v
  v -> ^
 A4 -> ZN
  combinational
  ^ -> v
  v -> ^
Cell AND2_X1
Library NangateOpenCellLibrary
File ../../test/nangate45/Nangate45_typ.lib
 VDD power
 VSS ground
 A1 input 0.87-0.92
 A2 input 0.89-0.97
 ZN output function=A1*A2

Timing arcs
 A1 -> ZN
  combinational
  ^ -> ^
  v -> v
 A2 -> ZN
  combinational
  ^ -> ^
  v -> v
Cell AND3_X1
Library NangateOpenCellLibrary
File ../../test/nangate45/Nangate45_typ.lib
 VDD power
 VSS ground
 A1 input 0.87-0.88
 A2 input 0.88-0.93
 A3 input 0.88-0.96
 ZN output function=(A1*A2)*A3

Timing arcs
 A1 -> ZN
  combinational
  ^ -> ^
  v -> v
 A2 -> ZN
  combinational
  ^ -> ^
  v -> v
 A3 -> ZN
  combinational
  ^ -> ^
  v -> v
Cell AND4_X1
Library NangateOpenCellLibrary
File ../../test/nangate45/Nangate45_typ.lib
 VDD power
 VSS ground
 A1 input 0.85-0.86
 A2 input 0.88-0.90
 A3 input 0.88-0.92
 A4 input 0.86-0.94
 ZN output function=((A1*A2)*A3)*A4

Timing arcs
 A1 -> ZN
  combinational
  ^ -> ^
  v -> v
 A2 -> ZN
  combinational
  ^ -> ^
  v -> v
 A3 -> ZN
  combinational
  ^ -> ^
  v -> v
 A4 -> ZN
  combinational
  ^ -> ^
  v -> v
Cell OR2_X1
Library NangateOpenCellLibrary
File ../../test/nangate45/Nangate45_typ.lib
 VDD power
 VSS ground
 A1 input 0.79-0.95
 A2 input 0.90-0.94
 ZN output function=A1+A2

Timing arcs
 A1 -> ZN
  combinational
  ^ -> ^
  v -> v
 A2 -> ZN
  combinational
  ^ -> ^
  v -> v
Cell OR3_X1
Library NangateOpenCellLibrary
File ../../test/nangate45/Nangate45_typ.lib
 VDD power
 VSS ground
 A1 input 0.78-0.96
 A2 input 0.85-0.94
 A3 input 0.90-0.92
 ZN output function=(A1+A2)+A3

Timing arcs
 A1 -> ZN
  combinational
  ^ -> ^
  v -> v
 A2 -> ZN
  combinational
  ^ -> ^
  v -> v
 A3 -> ZN
  combinational
  ^ -> ^
  v -> v
Cell OR4_X1
Library NangateOpenCellLibrary
File ../../test/nangate45/Nangate45_typ.lib
 VDD power
 VSS ground
 A1 input 0.75-0.94
 A2 input 0.83-0.94
 A3 input 0.85-0.92
 A4 input 0.89-0.91
 ZN output function=((A1+A2)+A3)+A4

Timing arcs
 A1 -> ZN
  combinational
  ^ -> ^
  v -> v
 A2 -> ZN
  combinational
  ^ -> ^
  v -> v
 A3 -> ZN
  combinational
  ^ -> ^
  v -> v
 A4 -> ZN
  combinational
  ^ -> ^
  v -> v
Cell ANTENNA_X1
Library NangateOpenCellLibrary
File ../../test/nangate45/Nangate45_typ.lib
 VDD power
 VSS ground
 A input 0.02-0.02
Cell FILLCELL_X1
Library NangateOpenCellLibrary
File ../../test/nangate45/Nangate45_typ.lib
 VDD power
 VSS ground
Cell LOGIC0_X1
Library NangateOpenCellLibrary
File ../../test/nangate45/Nangate45_typ.lib
 VDD power
 VSS ground
 Z output function=0
Cell LOGIC1_X1
Library NangateOpenCellLibrary
File ../../test/nangate45/Nangate45_typ.lib
 VDD power
 VSS ground
 Z output function=1
Cell CLKGATETST_X1
Library NangateOpenCellLibrary
File ../../test/nangate45/Nangate45_typ.lib
 VDD power
 VSS ground
 IQ internal
 CK input 1.67-1.81
 E input 0.84-0.88
 SE input 0.72-0.78
 GCK output

Timing arcs
 CK -> CK
  width
  v -> ^
 CK -> E
  hold
  ^ -> ^
  ^ -> v
 CK -> E
  setup
  ^ -> ^
  ^ -> v
 CK -> SE
  hold
  ^ -> ^
  ^ -> v
 CK -> SE
  setup
  ^ -> ^
  ^ -> v
 CK -> GCK
  combinational
  when !E*SE
  ^ -> ^
  v -> v
 CK -> GCK
  combinational
  when E*!SE
  ^ -> ^
  v -> v
 CK -> GCK
  combinational
  when E*SE
  ^ -> ^
  v -> v
 CK -> GCK
  combinational
  when !E*!SE
  v -> v
Cell CLKGATETST_X2
Library NangateOpenCellLibrary
File ../../test/nangate45/Nangate45_typ.lib
 VDD power
 VSS ground
 IQ internal
 CK input 2.63-2.82
 E input 0.84-0.87
 SE input 0.75-0.81
 GCK output

Timing arcs
 CK -> CK
  width
  v -> ^
 CK -> E
  hold
  ^ -> ^
  ^ -> v
 CK -> E
  setup
  ^ -> ^
  ^ -> v
 CK -> SE
  hold
  ^ -> ^
  ^ -> v
 CK -> SE
  setup
  ^ -> ^
  ^ -> v
 CK -> GCK
  combinational
  when !E*SE
  ^ -> ^
  v -> v
 CK -> GCK
  combinational
  when E*!SE
  ^ -> ^
  v -> v
 CK -> GCK
  combinational
  when E*SE
  ^ -> ^
  v -> v
 CK -> GCK
  combinational
  when !E*!SE
  v -> v
Cell SDFF_X1
Library NangateOpenCellLibrary
File ../../test/nangate45/Nangate45_typ.lib
 VDD power
 VSS ground
 D input 1.07-1.12
 SE input 1.76-1.89
 SI input 0.88-0.92
 CK input 0.87-0.96
 Q output function=IQ
 QN output function=IQN
 IQ internal
 IQN internal

Timing arcs
 CK -> D
  hold
  when !SE
  ^ -> ^
  ^ -> v
 CK -> D
  setup
  when !SE
  ^ -> ^
  ^ -> v
 CK -> SE
  hold
  ^ -> ^
  ^ -> v
 CK -> SE
  setup
  ^ -> ^
  ^ -> v
 CK -> SI
  hold
  when SE
  ^ -> ^
  ^ -> v
 CK -> SI
  setup
  when SE
  ^ -> ^
  ^ -> v
 CK -> CK
  width
  ^ -> v
  v -> ^
 CK -> Q
  Reg Clk to Q
  ^ -> ^
  ^ -> v
 CK -> QN
  Reg Clk to Q
  ^ -> ^
  ^ -> v
Cell SDFFR_X1
Library NangateOpenCellLibrary
File ../../test/nangate45/Nangate45_typ.lib
 VDD power
 VSS ground
 D input 1.10-1.15
 RN input 1.47-1.49
 SE input 1.88-2.00
 SI input 0.84-0.88
 CK input 0.94-1.03
 Q output function=IQ
 QN output function=IQN
 IQ internal
 IQN internal

Timing arcs
 CK -> D
  hold
  when RN*!SE
  ^ -> ^
  ^ -> v
 CK -> D
  setup
  when RN*!SE
  ^ -> ^
  ^ -> v
 CK -> RN
  recovery
  ^ -> ^
 CK -> RN
  removal
  ^ -> ^
 RN -> RN
  width
  v -> ^
 CK -> SE
  hold
  when RN
  ^ -> ^
  ^ -> v
 CK -> SE
  setup
  when RN
  ^ -> ^
  ^ -> v
 CK -> SI
  hold
  when RN*SE
  ^ -> ^
  ^ -> v
 CK -> SI
  setup
  when RN*SE
  ^ -> ^
  ^ -> v
 CK -> CK
  width
  when RN
  ^ -> v
  v -> ^
 CK -> Q
  Reg Clk to Q
  ^ -> ^
  ^ -> v
 RN -> Q
  Reg Set/Clr
  when ((!CK*!D)*!SE)*!SI
  v -> v
 RN -> Q
  Reg Set/Clr
  when ((!CK*!D)*!SE)*SI
  v -> v
 RN -> Q
  Reg Set/Clr
  when ((!CK*!D)*SE)*!SI
  v -> v
 RN -> Q
  Reg Set/Clr
  when ((!CK*!D)*SE)*SI
  v -> v
 RN -> Q
  Reg Set/Clr
  when ((!CK*D)*!SE)*!SI
  v -> v
 RN -> Q
  Reg Set/Clr
  when ((!CK*D)*!SE)*SI
  v -> v
 RN -> Q
  Reg Set/Clr
  when ((!CK*D)*SE)*!SI
  v -> v
 RN -> Q
  Reg Set/Clr
  when ((!CK*D)*SE)*SI
  v -> v
 RN -> Q
  Reg Set/Clr
  when ((CK*!D)*!SE)*!SI
  v -> v
 RN -> Q
  Reg Set/Clr
  when ((CK*!D)*!SE)*SI
  v -> v
 RN -> Q
  Reg Set/Clr
  when ((CK*!D)*SE)*!SI
  v -> v
 RN -> Q
  Reg Set/Clr
  when ((CK*!D)*SE)*SI
  v -> v
 RN -> Q
  Reg Set/Clr
  when ((CK*D)*!SE)*!SI
  v -> v
 RN -> Q
  Reg Set/Clr
  when ((CK*D)*!SE)*SI
  v -> v
 RN -> Q
  Reg Set/Clr
  when ((CK*D)*SE)*!SI
  v -> v
 RN -> Q
  Reg Set/Clr
  when ((CK*D)*SE)*SI
  v -> v
 CK -> QN
  Reg Clk to Q
  ^ -> ^
  ^ -> v
 RN -> QN
  Reg Set/Clr
  when ((!CK*!D)*!SE)*!SI
  v -> ^
 RN -> QN
  Reg Set/Clr
  when ((!CK*!D)*!SE)*SI
  v -> ^
 RN -> QN
  Reg Set/Clr
  when ((!CK*!D)*SE)*!SI
  v -> ^
 RN -> QN
  Reg Set/Clr
  when ((!CK*!D)*SE)*SI
  v -> ^
 RN -> QN
  Reg Set/Clr
  when ((!CK*D)*!SE)*!SI
  v -> ^
 RN -> QN
  Reg Set/Clr
  when ((!CK*D)*!SE)*SI
  v -> ^
 RN -> QN
  Reg Set/Clr
  when ((!CK*D)*SE)*!SI
  v -> ^
 RN -> QN
  Reg Set/Clr
  when ((!CK*D)*SE)*SI
  v -> ^
 RN -> QN
  Reg Set/Clr
  when ((CK*!D)*!SE)*!SI
  v -> ^
 RN -> QN
  Reg Set/Clr
  when ((CK*!D)*!SE)*SI
  v -> ^
 RN -> QN
  Reg Set/Clr
  when ((CK*!D)*SE)*!SI
  v -> ^
 RN -> QN
  Reg Set/Clr
  when ((CK*!D)*SE)*SI
  v -> ^
 RN -> QN
  Reg Set/Clr
  when ((CK*D)*!SE)*!SI
  v -> ^
 RN -> QN
  Reg Set/Clr
  when ((CK*D)*!SE)*SI
  v -> ^
 RN -> QN
  Reg Set/Clr
  when ((CK*D)*SE)*!SI
  v -> ^
 RN -> QN
  Reg Set/Clr
  when ((CK*D)*SE)*SI
  v -> ^
Cell SDFFS_X1
Library NangateOpenCellLibrary
File ../../test/nangate45/Nangate45_typ.lib
 VDD power
 VSS ground
 D input 1.10-1.15
 SE input 1.89-2.00
 SI input 0.86-0.90
 SN input 1.32-1.34
 CK input 0.89-0.98
 Q output function=IQ
 QN output function=IQN
 IQ internal
 IQN internal

Timing arcs
 CK -> D
  hold
  when !SE*SN
  ^ -> ^
  ^ -> v
 CK -> D
  setup
  when !SE*SN
  ^ -> ^
  ^ -> v
 CK -> SE
  hold
  when SN
  ^ -> ^
  ^ -> v
 CK -> SE
  setup
  when SN
  ^ -> ^
  ^ -> v
 CK -> SI
  hold
  when SE*SN
  ^ -> ^
  ^ -> v
 CK -> SI
  setup
  when SE*SN
  ^ -> ^
  ^ -> v
 CK -> SN
  recovery
  ^ -> ^
 CK -> SN
  removal
  ^ -> ^
 SN -> SN
  width
  v -> ^
 CK -> CK
  width
  when SN
  ^ -> v
  v -> ^
 CK -> Q
  Reg Clk to Q
  ^ -> ^
  ^ -> v
 SN -> Q
  Reg Set/Clr
  when ((!CK*!D)*!SE)*!SI
  v -> ^
 SN -> Q
  Reg Set/Clr
  when ((!CK*!D)*!SE)*SI
  v -> ^
 SN -> Q
  Reg Set/Clr
  when ((!CK*!D)*SE)*!SI
  v -> ^
 SN -> Q
  Reg Set/Clr
  when ((!CK*!D)*SE)*SI
  v -> ^
 SN -> Q
  Reg Set/Clr
  when ((!CK*D)*!SE)*!SI
  v -> ^
 SN -> Q
  Reg Set/Clr
  when ((!CK*D)*!SE)*SI
  v -> ^
 SN -> Q
  Reg Set/Clr
  when ((!CK*D)*SE)*!SI
  v -> ^
 SN -> Q
  Reg Set/Clr
  when ((!CK*D)*SE)*SI
  v -> ^
 SN -> Q
  Reg Set/Clr
  when ((CK*!D)*!SE)*!SI
  v -> ^
 SN -> Q
  Reg Set/Clr
  when ((CK*!D)*!SE)*SI
  v -> ^
 SN -> Q
  Reg Set/Clr
  when ((CK*!D)*SE)*!SI
  v -> ^
 SN -> Q
  Reg Set/Clr
  when ((CK*!D)*SE)*SI
  v -> ^
 SN -> Q
  Reg Set/Clr
  when ((CK*D)*!SE)*!SI
  v -> ^
 SN -> Q
  Reg Set/Clr
  when ((CK*D)*!SE)*SI
  v -> ^
 SN -> Q
  Reg Set/Clr
  when ((CK*D)*SE)*!SI
  v -> ^
 SN -> Q
  Reg Set/Clr
  when ((CK*D)*SE)*SI
  v -> ^
 CK -> QN
  Reg Clk to Q
  ^ -> ^
  ^ -> v
 SN -> QN
  Reg Set/Clr
  when ((!CK*!D)*!SE)*!SI
  v -> v
 SN -> QN
  Reg Set/Clr
  when ((!CK*!D)*!SE)*SI
  v -> v
 SN -> QN
  Reg Set/Clr
  when ((!CK*!D)*SE)*!SI
  v -> v
 SN -> QN
  Reg Set/Clr
  when ((!CK*!D)*SE)*SI
  v -> v
 SN -> QN
  Reg Set/Clr
  when ((!CK*D)*!SE)*!SI
  v -> v
 SN -> QN
  Reg Set/Clr
  when ((!CK*D)*!SE)*SI
  v -> v
 SN -> QN
  Reg Set/Clr
  when ((!CK*D)*SE)*!SI
  v -> v
 SN -> QN
  Reg Set/Clr
  when ((!CK*D)*SE)*SI
  v -> v
 SN -> QN
  Reg Set/Clr
  when ((CK*!D)*!SE)*!SI
  v -> v
 SN -> QN
  Reg Set/Clr
  when ((CK*!D)*!SE)*SI
  v -> v
 SN -> QN
  Reg Set/Clr
  when ((CK*!D)*SE)*!SI
  v -> v
 SN -> QN
  Reg Set/Clr
  when ((CK*!D)*SE)*SI
  v -> v
 SN -> QN
  Reg Set/Clr
  when ((CK*D)*!SE)*!SI
  v -> v
 SN -> QN
  Reg Set/Clr
  when ((CK*D)*!SE)*SI
  v -> v
 SN -> QN
  Reg Set/Clr
  when ((CK*D)*SE)*!SI
  v -> v
 SN -> QN
  Reg Set/Clr
  when ((CK*D)*SE)*SI
  v -> v
Cell SDFFRS_X1
Library NangateOpenCellLibrary
File ../../test/nangate45/Nangate45_typ.lib
 VDD power
 VSS ground
 D input 1.09-1.14
 RN input 2.13-2.25
 SE input 1.92-2.14
 SI input 0.82-0.86
 SN input 1.48-1.52
 CK input 0.86-0.95
 Q output function=IQ
 QN output function=IQN
 IQ internal
 IQN internal

Timing arcs
 CK -> D
  hold
  when (RN*!SE)*SN
  ^ -> ^
  ^ -> v
 CK -> D
  setup
  when (RN*!SE)*SN
  ^ -> ^
  ^ -> v
 CK -> RN
  recovery
  when SN
  ^ -> ^
 CK -> RN
  removal
  when SN
  ^ -> ^
 RN -> RN
  width
  when SN
  v -> ^
 CK -> SE
  hold
  when RN*SN
  ^ -> ^
  ^ -> v
 CK -> SE
  setup
  when RN*SN
  ^ -> ^
  ^ -> v
 CK -> SI
  hold
  when (RN*SE)*SN
  ^ -> ^
  ^ -> v
 CK -> SI
  setup
  when (RN*SE)*SN
  ^ -> ^
  ^ -> v
 CK -> SN
  recovery
  when RN
  ^ -> ^
 CK -> SN
  removal
  when RN
  ^ -> ^
 SN -> SN
  width
  when RN
  v -> ^
 CK -> CK
  width
  when RN*SN
  ^ -> v
  v -> ^
 CK -> Q
  Reg Clk to Q
  ^ -> ^
  ^ -> v
 RN -> Q
  Reg Set/Clr
  when (((!CK*!D)*!SE)*!SI)*!SN
  v -> v
 RN -> Q
  Reg Set/Clr
  when (((!CK*!D)*!SE)*!SI)*SN
  v -> v
 RN -> Q
  Reg Set/Clr
  when (((!CK*!D)*!SE)*SI)*!SN
  v -> v
 RN -> Q
  Reg Set/Clr
  when (((!CK*!D)*!SE)*SI)*SN
  v -> v
 RN -> Q
  Reg Set/Clr
  when (((!CK*!D)*SE)*!SI)*!SN
  v -> v
 RN -> Q
  Reg Set/Clr
  when (((!CK*!D)*SE)*!SI)*SN
  v -> v
 RN -> Q
  Reg Set/Clr
  when (((!CK*!D)*SE)*SI)*!SN
  v -> v
 RN -> Q
  Reg Set/Clr
  when (((!CK*!D)*SE)*SI)*SN
  v -> v
 RN -> Q
  Reg Set/Clr
  when (((!CK*D)*!SE)*!SI)*!SN
  v -> v
 RN -> Q
  Reg Set/Clr
  when (((!CK*D)*!SE)*!SI)*SN
  v -> v
 RN -> Q
  Reg Set/Clr
  when (((!CK*D)*!SE)*SI)*!SN
  v -> v
 RN -> Q
  Reg Set/Clr
  when (((!CK*D)*!SE)*SI)*SN
  v -> v
 RN -> Q
  Reg Set/Clr
  when (((!CK*D)*SE)*!SI)*!SN
  v -> v
 RN -> Q
  Reg Set/Clr
  when (((!CK*D)*SE)*!SI)*SN
  v -> v
 RN -> Q
  Reg Set/Clr
  when (((!CK*D)*SE)*SI)*!SN
  v -> v
 RN -> Q
  Reg Set/Clr
  when (((!CK*D)*SE)*SI)*SN
  v -> v
 RN -> Q
  Reg Set/Clr
  when (((CK*!D)*!SE)*!SI)*!SN
  v -> v
 RN -> Q
  Reg Set/Clr
  when (((CK*!D)*!SE)*!SI)*SN
  v -> v
 RN -> Q
  Reg Set/Clr
  when (((CK*!D)*!SE)*SI)*!SN
  v -> v
 RN -> Q
  Reg Set/Clr
  when (((CK*!D)*!SE)*SI)*SN
  v -> v
 RN -> Q
  Reg Set/Clr
  when (((CK*!D)*SE)*!SI)*!SN
  v -> v
 RN -> Q
  Reg Set/Clr
  when (((CK*!D)*SE)*!SI)*SN
  v -> v
 RN -> Q
  Reg Set/Clr
  when (((CK*!D)*SE)*SI)*!SN
  v -> v
 RN -> Q
  Reg Set/Clr
  when (((CK*!D)*SE)*SI)*SN
  v -> v
 RN -> Q
  Reg Set/Clr
  when (((CK*D)*!SE)*!SI)*!SN
  v -> v
 RN -> Q
  Reg Set/Clr
  when (((CK*D)*!SE)*!SI)*SN
  v -> v
 RN -> Q
  Reg Set/Clr
  when (((CK*D)*!SE)*SI)*!SN
  v -> v
 RN -> Q
  Reg Set/Clr
  when (((CK*D)*!SE)*SI)*SN
  v -> v
 RN -> Q
  Reg Set/Clr
  when (((CK*D)*SE)*!SI)*!SN
  v -> v
 RN -> Q
  Reg Set/Clr
  when (((CK*D)*SE)*!SI)*SN
  v -> v
 RN -> Q
  Reg Set/Clr
  when (((CK*D)*SE)*SI)*!SN
  v -> v
 RN -> Q
  Reg Set/Clr
  when (((CK*D)*SE)*SI)*SN
  v -> v
 SN -> Q
  Reg Set/Clr
  when (((!CK*!D)*RN)*!SE)*!SI
  v -> ^
 SN -> Q
  Reg Set/Clr
  when (((!CK*!D)*RN)*!SE)*SI
  v -> ^
 SN -> Q
  Reg Set/Clr
  when (((!CK*!D)*RN)*SE)*!SI
  v -> ^
 SN -> Q
  Reg Set/Clr
  when (((!CK*!D)*RN)*SE)*SI
  v -> ^
 SN -> Q
  Reg Set/Clr
  when (((!CK*D)*RN)*!SE)*!SI
  v -> ^
 SN -> Q
  Reg Set/Clr
  when (((!CK*D)*RN)*!SE)*SI
  v -> ^
 SN -> Q
  Reg Set/Clr
  when (((!CK*D)*RN)*SE)*!SI
  v -> ^
 SN -> Q
  Reg Set/Clr
  when (((!CK*D)*RN)*SE)*SI
  v -> ^
 SN -> Q
  Reg Set/Clr
  when (((CK*!D)*RN)*!SE)*!SI
  v -> ^
 SN -> Q
  Reg Set/Clr
  when (((CK*!D)*RN)*!SE)*SI
  v -> ^
 SN -> Q
  Reg Set/Clr
  when (((CK*!D)*RN)*SE)*!SI
  v -> ^
 SN -> Q
  Reg Set/Clr
  when (((CK*!D)*RN)*SE)*SI
  v -> ^
 SN -> Q
  Reg Set/Clr
  when (((CK*D)*RN)*!SE)*!SI
  v -> ^
 SN -> Q
  Reg Set/Clr
  when (((CK*D)*RN)*!SE)*SI
  v -> ^
 SN -> Q
  Reg Set/Clr
  when (((CK*D)*RN)*SE)*!SI
  v -> ^
 SN -> Q
  Reg Set/Clr
  when (((CK*D)*RN)*SE)*SI
  v -> ^
 CK -> QN
  Reg Clk to Q
  ^ -> ^
  ^ -> v
 RN -> QN
  Reg Set/Clr
  when (((!CK*!D)*!SE)*!SI)*SN
  v -> ^
 RN -> QN
  Reg Set/Clr
  when (((!CK*!D)*!SE)*SI)*SN
  v -> ^
 RN -> QN
  Reg Set/Clr
  when (((!CK*!D)*SE)*!SI)*SN
  v -> ^
 RN -> QN
  Reg Set/Clr
  when (((!CK*!D)*SE)*SI)*SN
  v -> ^
 RN -> QN
  Reg Set/Clr
  when (((!CK*D)*!SE)*!SI)*SN
  v -> ^
 RN -> QN
  Reg Set/Clr
  when (((!CK*D)*!SE)*SI)*SN
  v -> ^
 RN -> QN
  Reg Set/Clr
  when (((!CK*D)*SE)*!SI)*SN
  v -> ^
 RN -> QN
  Reg Set/Clr
  when (((!CK*D)*SE)*SI)*SN
  v -> ^
 RN -> QN
  Reg Set/Clr
  when (((CK*!D)*!SE)*!SI)*SN
  v -> ^
 RN -> QN
  Reg Set/Clr
  when (((CK*!D)*!SE)*SI)*SN
  v -> ^
 RN -> QN
  Reg Set/Clr
  when (((CK*!D)*SE)*!SI)*SN
  v -> ^
 RN -> QN
  Reg Set/Clr
  when (((CK*!D)*SE)*SI)*SN
  v -> ^
 RN -> QN
  Reg Set/Clr
  when (((CK*D)*!SE)*!SI)*SN
  v -> ^
 RN -> QN
  Reg Set/Clr
  when (((CK*D)*!SE)*SI)*SN
  v -> ^
 RN -> QN
  Reg Set/Clr
  when (((CK*D)*SE)*!SI)*SN
  v -> ^
 RN -> QN
  Reg Set/Clr
  when (((CK*D)*SE)*SI)*SN
  v -> ^
 SN -> QN
  Reg Set/Clr
  when (((!CK*!D)*!RN)*!SE)*!SI
  v -> v
 SN -> QN
  Reg Set/Clr
  when (((!CK*!D)*!RN)*!SE)*SI
  v -> v
 SN -> QN
  Reg Set/Clr
  when (((!CK*!D)*!RN)*SE)*!SI
  v -> v
 SN -> QN
  Reg Set/Clr
  when (((!CK*!D)*!RN)*SE)*SI
  v -> v
 SN -> QN
  Reg Set/Clr
  when (((!CK*!D)*RN)*!SE)*!SI
  v -> v
 SN -> QN
  Reg Set/Clr
  when (((!CK*!D)*RN)*!SE)*SI
  v -> v
 SN -> QN
  Reg Set/Clr
  when (((!CK*!D)*RN)*SE)*!SI
  v -> v
 SN -> QN
  Reg Set/Clr
  when (((!CK*!D)*RN)*SE)*SI
  v -> v
 SN -> QN
  Reg Set/Clr
  when (((!CK*D)*!RN)*!SE)*!SI
  v -> v
 SN -> QN
  Reg Set/Clr
  when (((!CK*D)*!RN)*!SE)*SI
  v -> v
 SN -> QN
  Reg Set/Clr
  when (((!CK*D)*!RN)*SE)*!SI
  v -> v
 SN -> QN
  Reg Set/Clr
  when (((!CK*D)*!RN)*SE)*SI
  v -> v
 SN -> QN
  Reg Set/Clr
  when (((!CK*D)*RN)*!SE)*!SI
  v -> v
 SN -> QN
  Reg Set/Clr
  when (((!CK*D)*RN)*!SE)*SI
  v -> v
 SN -> QN
  Reg Set/Clr
  when (((!CK*D)*RN)*SE)*!SI
  v -> v
 SN -> QN
  Reg Set/Clr
  when (((!CK*D)*RN)*SE)*SI
  v -> v
 SN -> QN
  Reg Set/Clr
  when (((CK*!D)*!RN)*!SE)*!SI
  v -> v
 SN -> QN
  Reg Set/Clr
  when (((CK*!D)*!RN)*!SE)*SI
  v -> v
 SN -> QN
  Reg Set/Clr
  when (((CK*!D)*!RN)*SE)*!SI
  v -> v
 SN -> QN
  Reg Set/Clr
  when (((CK*!D)*!RN)*SE)*SI
  v -> v
 SN -> QN
  Reg Set/Clr
  when (((CK*!D)*RN)*!SE)*!SI
  v -> v
 SN -> QN
  Reg Set/Clr
  when (((CK*!D)*RN)*!SE)*SI
  v -> v
 SN -> QN
  Reg Set/Clr
  when (((CK*!D)*RN)*SE)*!SI
  v -> v
 SN -> QN
  Reg Set/Clr
  when (((CK*!D)*RN)*SE)*SI
  v -> v
 SN -> QN
  Reg Set/Clr
  when (((CK*D)*!RN)*!SE)*!SI
  v -> v
 SN -> QN
  Reg Set/Clr
  when (((CK*D)*!RN)*!SE)*SI
  v -> v
 SN -> QN
  Reg Set/Clr
  when (((CK*D)*!RN)*SE)*!SI
  v -> v
 SN -> QN
  Reg Set/Clr
  when (((CK*D)*!RN)*SE)*SI
  v -> v
 SN -> QN
  Reg Set/Clr
  when (((CK*D)*RN)*!SE)*!SI
  v -> v
 SN -> QN
  Reg Set/Clr
  when (((CK*D)*RN)*!SE)*SI
  v -> v
 SN -> QN
  Reg Set/Clr
  when (((CK*D)*RN)*SE)*!SI
  v -> v
 SN -> QN
  Reg Set/Clr
  when (((CK*D)*RN)*SE)*SI
  v -> v
Cell DFFHQNx1_ASAP7_75t_R
Library asap7sc7p5t_SEQ_RVT_FF_nldm_220123
File ../../test/asap7/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib
 VDD power
 VSS ground
 QN output function=IQN
 CLK input 0.40-0.52
 D input 0.55-0.62
 IQN internal
 IQNN internal

Timing arcs
 CLK -> QN
  Reg Clk to Q
  ^ -> ^
  ^ -> v
 CLK -> CLK
  width
  when D
  ^ -> v
  v -> ^
 CLK -> CLK
  width
  when !D
  ^ -> v
  v -> ^
 CLK -> D
  hold
  ^ -> ^
  ^ -> v
 CLK -> D
  setup
  ^ -> ^
  ^ -> v
Cell ICGx1_ASAP7_75t_R
Library asap7sc7p5t_SEQ_RVT_FF_nldm_220123
File ../../test/asap7/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib
 VDD power
 VSS ground
 IQ internal
 GCLK output
 CLK input 1.63-2.39
 ENA input 0.33-0.47
 SE input 0.39-0.47

Timing arcs
 CLK -> GCLK
  combinational
  when ENA+(!ENA*SE)
  v -> v
 CLK -> GCLK
  combinational
  when !ENA*!SE
  v -> v
 CLK -> GCLK
  combinational
  ^ -> ^
  v -> v
 CLK -> CLK
  width
  when ENA+(!ENA*SE)
  ^ -> v
  v -> ^
 CLK -> CLK
  width
  when !ENA*!SE
  v -> ^
 CLK -> ENA
  hold
  when !SE
  ^ -> ^
  ^ -> v
 CLK -> ENA
  hold
  ^ -> ^
  ^ -> v
 CLK -> ENA
  setup
  when !SE
  ^ -> ^
  ^ -> v
 CLK -> ENA
  setup
  ^ -> ^
  ^ -> v
 CLK -> SE
  hold
  when !ENA
  ^ -> ^
  ^ -> v
 CLK -> SE
  hold
  ^ -> ^
  ^ -> v
 CLK -> SE
  setup
  when !ENA
  ^ -> ^
  ^ -> v
 CLK -> SE
  setup
  ^ -> ^
  ^ -> v
Cell sg13g2_ebufn_2
Library sg13g2_stdcell_typ_1p20V_25C
File ../../test/ihp-sg13g2/sg13g2_stdcell_typ_1p20V_25C.lib
 Z tristate enable=!TE_B function=A 4.51-7.42
 A input 2.58-2.66
 TE_B input 6.21-6.60

Timing arcs
 A -> Z
  combinational
  ^ -> ^
  v -> v
 TE_B -> Z
  tristate disable
  ^ -> 0Z
  ^ -> 1Z
 TE_B -> Z
  tristate enable
  v -> Z1
  v -> Z0
Cell sg13g2_sdfbbp_1
Library sg13g2_stdcell_typ_1p20V_25C
File ../../test/ihp-sg13g2/sg13g2_stdcell_typ_1p20V_25C.lib
 Q output function=IQ
 Q_N output function=IQN
 CLK input 2.97-3.06
 D input 1.95-2.01
 RESET_B input 1.74
 SCD input 1.96-2.00
 SCE input 3.18-3.92
 SET_B input 5.25
 IQ internal
 IQN internal

Timing arcs
 CLK -> Q
  Reg Clk to Q
  when SCE
  ^ -> ^
  ^ -> v
 CLK -> Q
  Reg Clk to Q
  ^ -> ^
  ^ -> v
 RESET_B -> Q
  Reg Set/Clr
  v -> v
 SET_B -> Q
  Reg Set/Clr
  v -> ^
 CLK -> Q_N
  Reg Clk to Q
  when SCE
  ^ -> ^
  ^ -> v
 CLK -> Q_N
  Reg Clk to Q
  ^ -> ^
  ^ -> v
 RESET_B -> Q_N
  Reg Set/Clr
  v -> ^
 SET_B -> Q_N
  Reg Set/Clr
  v -> v
 CLK -> CLK
  width
  ^ -> v
  v -> ^
 CLK -> D
  hold
  ^ -> ^
  ^ -> v
 CLK -> D
  setup
  ^ -> ^
  ^ -> v
 CLK -> RESET_B
  recovery
  ^ -> ^
 CLK -> RESET_B
  removal
  ^ -> ^
 RESET_B -> RESET_B
  width
  v -> ^
 CLK -> SCD
  hold
  ^ -> ^
  ^ -> v
 CLK -> SCD
  setup
  ^ -> ^
  ^ -> v
 CLK -> SCE
  hold
  ^ -> ^
  ^ -> v
 CLK -> SCE
  setup
  ^ -> ^
  ^ -> v
 CLK -> SET_B
  recovery
  ^ -> ^
 CLK -> SET_B
  removal
  ^ -> ^
 RESET_B -> SET_B
  non-sequential hold
  ^ -> ^
 RESET_B -> SET_B
  non-sequential setup
  ^ -> ^
 SET_B -> SET_B
  width
  v -> ^
Cell sky130_fd_sc_hd__inv_1
Library sky130_fd_sc_hd__tt_025C_1v80
File ../../test/sky130hd/sky130hd_tt.lib
 VGND ground
 VNB bias
 VPB bias
 VPWR power
 A input 2.21-2.39
 Y output function=!A

Timing arcs
 A -> Y
  combinational
  ^ -> v
  v -> ^