Logo
Explore Help
Sign In
luke/OpenSTA
Watch 1
Star 0
Fork 0
mirror of https://github.com/The-OpenROAD-Project/OpenSTA.git synced 2026-09-03 08:25:52 +02:00
Code Issues Packages Projects Releases Wiki Activity
Files
2a2b5cd59f5d1b596f20cbd39609c52b33299e06
OpenSTA/verilog
T
History
James Cherry 1af03c8d0f write_verilog -remove_cells support non-liberty cells
Signed-off-by: James Cherry <[email protected]>
2023-01-04 11:22:23 -07:00
..
Verilog.i
write_verilog -remove_cells support non-liberty cells
2023-01-04 11:22:23 -07:00
Verilog.tcl
write_verilog -remove_cells support non-liberty cells
2023-01-04 11:22:23 -07:00
VerilogLex.ll
update copyright
2022-01-04 10:17:08 -07:00
VerilogParse.yy
update copyright
2022-01-04 10:17:08 -07:00
VerilogReader.cc
liberty warnings for zero default_max_transition default_fanout_load
2022-04-03 13:13:06 -07:00
VerilogReaderPvt.hh
flush DISALLOW_COPY_AND_ASSIGN
2022-02-19 18:31:52 -07:00
VerilogWriter.cc
write_verilog -remove_cells support non-liberty cells
2023-01-04 11:22:23 -07:00
Powered by Gitea Version: 1.27.2 Page: 49ms Template: 1ms
Auto
English
Bahasa Indonesia Deutsch English Español Français Gaeilge Italiano Latviešu Magyar nyelv Nederlands Polski Português de Portugal Português do Brasil Suomi Svenska Türkçe Čeština Ελληνικά Български Русский Українська فارسی മലയാളം 日本語 简体中文 繁體中文(台灣) 繁體中文(香港) 한국어
Licenses API