137 lines
4.7 KiB
Plaintext
137 lines
4.7 KiB
Plaintext
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
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Endpoint: out1 (output port clocked by clk1)
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Path Group: clk1
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk1 (rise edge)
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0.60 0.60 clock network delay (ideal)
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0.00 0.60 ^ reg2/CK (DFF_X1)
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0.08 0.68 ^ reg2/Q (DFF_X1)
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0.00 0.68 ^ out1 (out)
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0.68 data arrival time
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10.00 10.00 clock clk1 (rise edge)
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0.25 10.25 clock network delay (ideal)
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-0.20 10.05 clock uncertainty
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0.00 10.05 clock reconvergence pessimism
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-3.00 7.05 output external delay
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7.05 data required time
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---------------------------------------------------------
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7.05 data required time
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-0.68 data arrival time
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---------------------------------------------------------
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6.37 slack (MET)
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Startpoint: reg3/Q (clock source 'gclk2')
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Endpoint: out2 (output port clocked by clk2)
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Path Group: clk2
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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16.67 16.67 clock gclk2 (fall edge)
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0.00 16.67 clock network delay
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16.67 v out2 (out)
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16.67 data arrival time
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20.00 20.00 clock clk2 (rise edge)
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0.20 20.20 clock network delay (ideal)
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0.00 20.20 clock reconvergence pessimism
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-3.50 16.70 output external delay
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16.70 data required time
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---------------------------------------------------------
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16.70 data required time
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-16.67 data arrival time
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---------------------------------------------------------
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0.03 slack (MET)
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Warning 101: sdc_remove_clock_gating.tcl line 1, object 'sdc_test2' not found.
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Warning 101: sdc_remove_clock_gating.tcl line 1, object 'sdc_test2' not found.
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Clock Period Waveform
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----------------------------------------------------
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clk1 10.00 0.00 5.00
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Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
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Endpoint: out1 (output port clocked by clk1)
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Path Group: clk1
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk1 (rise edge)
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0.60 0.60 clock network delay (ideal)
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0.00 0.60 ^ reg2/CK (DFF_X1)
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0.08 0.68 ^ reg2/Q (DFF_X1)
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0.00 0.68 ^ out1 (out)
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0.68 data arrival time
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10.00 10.00 clock clk1 (rise edge)
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0.25 10.25 clock network delay (ideal)
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-0.20 10.05 clock uncertainty
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0.00 10.05 clock reconvergence pessimism
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-3.00 7.05 output external delay
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7.05 data required time
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---------------------------------------------------------
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7.05 data required time
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-0.68 data arrival time
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---------------------------------------------------------
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6.37 slack (MET)
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Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
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Endpoint: out1 (output port clocked by clk1)
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Path Group: clk1
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk1 (rise edge)
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0.60 0.60 clock network delay (ideal)
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0.00 0.60 ^ reg2/CK (DFF_X1)
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0.08 0.68 ^ reg2/Q (DFF_X1)
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0.00 0.68 ^ out1 (out)
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0.68 data arrival time
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10.00 10.00 clock clk1 (rise edge)
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0.25 10.25 clock network delay (ideal)
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-0.20 10.05 clock uncertainty
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0.00 10.05 clock reconvergence pessimism
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-3.00 7.05 output external delay
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7.05 data required time
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---------------------------------------------------------
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7.05 data required time
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-0.68 data arrival time
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---------------------------------------------------------
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6.37 slack (MET)
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Startpoint: reg3 (rising edge-triggered flip-flop clocked by clk2_new)
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Endpoint: out2 (output port clocked by clk2_new)
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Path Group: clk2_new
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk2_new (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg3/CK (DFF_X1)
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0.08 0.08 ^ reg3/Q (DFF_X1)
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0.00 0.08 ^ out2 (out)
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0.08 data arrival time
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15.00 15.00 clock clk2_new (rise edge)
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0.00 15.00 clock network delay (ideal)
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0.00 15.00 clock reconvergence pessimism
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-2.50 12.50 output external delay
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12.50 data required time
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---------------------------------------------------------
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12.50 data required time
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-0.08 data arrival time
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---------------------------------------------------------
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12.42 slack (MET)
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