161 lines
4.0 KiB
Plaintext
161 lines
4.0 KiB
Plaintext
--- get_fanin -to output pin -flat ---
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fanin flat pin count: 3
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--- get_fanin -to output pin -only_cells ---
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fanin cells count: 2
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--- get_fanin -to output pin -startpoints_only ---
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fanin startpoints count: 1
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--- get_fanout -from input pin -flat ---
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fanout flat pin count: 6
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--- get_fanout -from input pin -only_cells ---
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fanout cells count: 4
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--- get_fanout -from input pin -endpoints_only ---
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fanout endpoints count: 1
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--- get_fanin with -trace_arcs timing ---
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fanin timing trace count: 3
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--- get_fanin with -trace_arcs enabled ---
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fanin enabled trace count: 3
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--- get_fanin with -trace_arcs all ---
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fanin all trace count: 3
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--- get_fanout with -trace_arcs all ---
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fanout all trace count: 6
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--- get_fanin with -levels ---
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fanin levels=1 count: 3
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--- get_fanin with -pin_levels ---
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fanin pin_levels=2 count: 3
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--- get_fanout with -levels ---
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fanout levels=1 count: 3
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--- get_fanout with -pin_levels ---
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fanout pin_levels=2 count: 3
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--- get_cells -hierarchical ---
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hierarchical cells count: 3
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--- get_nets -hierarchical ---
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hierarchical nets count: 6
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--- get_pins -hierarchical ---
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hierarchical pins count: 11
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--- report_instance buf1 ---
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Instance buf1
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Cell: BUF_X1
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Library: NangateOpenCellLibrary
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Path cells: BUF_X1
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Input pins:
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A input in1
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Output pins:
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Z output n1
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Other pins:
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VDD power (unconnected)
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VSS ground (unconnected)
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--- report_instance and1 ---
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Instance and1
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Cell: AND2_X1
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Library: NangateOpenCellLibrary
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Path cells: AND2_X1
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Input pins:
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A1 input n1
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A2 input in2
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Output pins:
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ZN output n2
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Other pins:
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VDD power (unconnected)
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VSS ground (unconnected)
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--- report_instance reg1 ---
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Instance reg1
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Cell: DFF_X1
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Library: NangateOpenCellLibrary
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Path cells: DFF_X1
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Input pins:
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D input n2
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CK input clk
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Output pins:
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Q output out1
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QN output (unconnected)
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Other pins:
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VDD power (unconnected)
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VSS ground (unconnected)
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IQ internal (unconnected)
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IQN internal (unconnected)
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--- report_net n1 ---
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Net n1
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Pin capacitance: 0.87-0.92
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Wire capacitance: 0.00
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Total capacitance: 0.87-0.92
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Number of drivers: 1
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Number of loads: 1
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Number of pins: 2
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Driver pins
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buf1/Z output (BUF_X1)
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Load pins
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and1/A1 input (AND2_X1) 0.87-0.92
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--- report_net n2 ---
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Net n2
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Pin capacitance: 1.06-1.14
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Wire capacitance: 0.00
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Total capacitance: 1.06-1.14
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Number of drivers: 1
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Number of loads: 1
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Number of pins: 2
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Driver pins
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and1/ZN output (AND2_X1)
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Load pins
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reg1/D input (DFF_X1) 1.06-1.14
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--- get_full_name / get_name for instances ---
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buf1 full_name: buf1
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buf1 name: buf1
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--- get_full_name / get_name for nets ---
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n1 full_name: n1
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n1 name: n1
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--- get_full_name / get_name for pins ---
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buf1/A full_name: buf1/A
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--- get_full_name / get_name for ports ---
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in1 full_name: in1
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in1 name: in1
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--- all_inputs ---
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all_inputs count: 3
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--- all_outputs ---
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all_outputs count: 1
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--- all_clocks ---
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all_clocks count: 1
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--- get_ports -filter direction == input ---
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input ports count: 3
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--- get_cells -filter ref_name == BUF_X1 ---
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BUF_X1 cells count: 1
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--- get_cells -filter ref_name == AND2_X1 ---
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AND2_X1 cells count: 1
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--- get_cells -filter ref_name == DFF_X1 ---
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DFF_X1 cells count: 1
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--- report_checks to verify timing graph ---
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Startpoint: in1 (input port clocked by clk)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v in1 (in)
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0.02 0.02 v buf1/Z (BUF_X1)
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0.02 0.05 v and1/ZN (AND2_X1)
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0.00 0.05 v reg1/D (DFF_X1)
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0.05 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg1/CK (DFF_X1)
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-0.04 9.96 library setup time
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9.96 data required time
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---------------------------------------------------------
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9.96 data required time
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-0.05 data arrival time
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---------------------------------------------------------
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9.92 slack (MET)
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