340 lines
9.8 KiB
Plaintext
340 lines
9.8 KiB
Plaintext
Startpoint: in1 (input port clocked by clk)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v in1 (in)
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2.03 2.03 v buf1/Z (BUF_X1)
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0.10 2.13 v and1/ZN (AND2_X1)
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0.00 2.13 v reg1/D (DFF_X1)
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2.13 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg1/CK (DFF_X1)
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-0.13 9.87 library setup time
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9.87 data required time
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---------------------------------------------------------
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9.87 data required time
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-2.13 data arrival time
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---------------------------------------------------------
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7.74 slack (MET)
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--- instance sorting ---
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total cells: 3
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cells in order:
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and1 ref=AND2_X1
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buf1 ref=BUF_X1
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reg1 ref=DFF_X1
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--- net sorting ---
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total nets: 6
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nets in order:
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clk
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in1
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in2
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n1
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n2
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out1
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--- port sorting ---
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total ports: 4
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ports in order:
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clk dir=input
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in1 dir=input
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in2 dir=input
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out1 dir=output
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--- pin sorting ---
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total pins: 11
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pins in order:
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and1/A1 dir=input
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and1/A2 dir=input
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and1/ZN dir=output
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buf1/A dir=input
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buf1/Z dir=output
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reg1/D dir=input
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reg1/CK dir=input
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reg1/Q dir=output
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reg1/QN dir=output
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reg1/IQ dir=internal
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reg1/IQN dir=internal
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--- collection operations ---
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buf1 pins: 2
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and1 pins: 3
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reg1 pins: 6
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--- timing report sorting ---
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Warning 168: network_sorting.tcl line 1, unknown field nets.
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Startpoint: in1 (input port clocked by clk)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Fanout Cap Slew Delay Time Description
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-----------------------------------------------------------------------------
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0.00 0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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1 0.88 10.00 0.00 0.00 v in1 (in)
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10.00 0.00 0.00 v buf1/A (BUF_X1)
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1 0.87 0.32 2.03 2.03 v buf1/Z (BUF_X1)
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0.32 0.00 2.03 v and1/A1 (AND2_X1)
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1 1.06 0.30 0.10 2.13 v and1/ZN (AND2_X1)
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0.30 0.00 2.13 v reg1/D (DFF_X1)
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2.13 data arrival time
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0.00 10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg1/CK (DFF_X1)
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-0.13 9.87 library setup time
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9.87 data required time
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-----------------------------------------------------------------------------
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9.87 data required time
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-2.13 data arrival time
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-----------------------------------------------------------------------------
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7.74 slack (MET)
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Warning 168: network_sorting.tcl line 1, unknown field nets.
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Startpoint: in1 (input port clocked by clk)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: min
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Fanout Cap Slew Delay Time Description
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-----------------------------------------------------------------------------
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0.00 0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ input external delay
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1 0.97 10.00 0.00 0.00 ^ in1 (in)
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10.00 0.00 0.00 ^ buf1/A (BUF_X1)
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1 0.92 0.31 -0.18 -0.18 ^ buf1/Z (BUF_X1)
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0.31 0.00 -0.18 ^ and1/A1 (AND2_X1)
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1 1.14 0.02 0.06 -0.12 ^ and1/ZN (AND2_X1)
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0.02 0.00 -0.12 ^ reg1/D (DFF_X1)
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-0.12 data arrival time
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0.00 0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 ^ reg1/CK (DFF_X1)
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0.01 0.01 library hold time
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0.01 data required time
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-----------------------------------------------------------------------------
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0.01 data required time
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0.12 data arrival time
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-----------------------------------------------------------------------------
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-0.13 slack (VIOLATED)
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Startpoint: in1 (input port clocked by clk)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v in1 (in)
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2.03 2.03 v buf1/Z (BUF_X1)
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0.10 2.13 v and1/ZN (AND2_X1)
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0.00 2.13 v reg1/D (DFF_X1)
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2.13 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg1/CK (DFF_X1)
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-0.13 9.87 library setup time
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9.87 data required time
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---------------------------------------------------------
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9.87 data required time
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-2.13 data arrival time
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---------------------------------------------------------
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7.74 slack (MET)
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Startpoint: in1 (input port clocked by clk)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v in1 (in)
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2.03 2.03 v buf1/Z (BUF_X1)
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0.10 2.13 v and1/ZN (AND2_X1)
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0.00 2.13 v reg1/D (DFF_X1)
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2.13 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg1/CK (DFF_X1)
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-0.13 9.87 library setup time
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9.87 data required time
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---------------------------------------------------------
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9.87 data required time
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-2.13 data arrival time
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---------------------------------------------------------
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7.74 slack (MET)
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: out1 (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg1/CK (DFF_X1)
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0.08 0.08 ^ reg1/Q (DFF_X1)
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0.00 0.08 ^ out1 (out)
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0.08 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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0.00 10.00 output external delay
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10.00 data required time
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---------------------------------------------------------
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10.00 data required time
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-0.08 data arrival time
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---------------------------------------------------------
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9.92 slack (MET)
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--- report_net sorted ---
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Net n1
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Pin capacitance: 0.87-0.92
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Wire capacitance: 0.00
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Total capacitance: 0.87-0.92
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Number of drivers: 1
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Number of loads: 1
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Number of pins: 2
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Driver pins
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buf1/Z output (BUF_X1)
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Load pins
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and1/A1 input (AND2_X1) 0.87-0.92
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Net n2
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Pin capacitance: 1.06-1.14
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Wire capacitance: 0.00
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Total capacitance: 1.06-1.14
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Number of drivers: 1
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Number of loads: 1
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Number of pins: 2
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Driver pins
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and1/ZN output (AND2_X1)
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Load pins
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reg1/D input (DFF_X1) 1.06-1.14
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Net n1
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Pin capacitance: 0.87-0.92
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Wire capacitance: 0.00
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Total capacitance: 0.87-0.92
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Number of drivers: 1
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Number of loads: 1
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Number of pins: 2
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Driver pins
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buf1/Z output (BUF_X1)
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Load pins
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and1/A1 input (AND2_X1) 0.87-0.92
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Net n2
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Pin capacitance: 1.0623-1.1403
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Wire capacitance: 0.0000
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Total capacitance: 1.0623-1.1403
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Number of drivers: 1
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Number of loads: 1
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Number of pins: 2
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Driver pins
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and1/ZN output (AND2_X1)
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Load pins
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reg1/D input (DFF_X1) 1.0623-1.1403
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Net n1
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Pin capacitance: 0.874832-0.918145
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Wire capacitance: 0.000000
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Total capacitance: 0.874832-0.918145
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Number of drivers: 1
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Number of loads: 1
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Number of pins: 2
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Driver pins
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buf1/Z output (BUF_X1)
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Load pins
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and1/A1 input (AND2_X1) 0.874832-0.918145
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--- report_instance sorted ---
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Instance and1
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Cell: AND2_X1
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Library: NangateOpenCellLibrary
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Path cells: AND2_X1
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Input pins:
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A1 input n1
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A2 input in2
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Output pins:
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ZN output n2
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Other pins:
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VDD power (unconnected)
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VSS ground (unconnected)
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Instance buf1
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Cell: BUF_X1
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Library: NangateOpenCellLibrary
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Path cells: BUF_X1
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Input pins:
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A input in1
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Output pins:
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Z output n1
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Other pins:
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VDD power (unconnected)
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VSS ground (unconnected)
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Instance reg1
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Cell: DFF_X1
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Library: NangateOpenCellLibrary
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Path cells: DFF_X1
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Input pins:
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D input n2
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CK input clk
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Output pins:
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Q output out1
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QN output (unconnected)
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Other pins:
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VDD power (unconnected)
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VSS ground (unconnected)
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IQ internal (unconnected)
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IQN internal (unconnected)
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--- property queries ---
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buf1 full_name: buf1
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buf1 ref_name: BUF_X1
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n1 full_name: n1
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buf1/A full_name: buf1/A
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buf1/A direction: input
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in1 full_name: in1
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in1 direction: input
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--- library queries ---
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libraries: 1
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lib: NangateOpenCellLibrary
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