264 lines
8.3 KiB
Plaintext
264 lines
8.3 KiB
Plaintext
--- Test 1: SDC namespace with flat design ---
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sdc ports: 11
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sdc cells: 12
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sdc nets: 19
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sdc data_in[*]: 4
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sdc data_out[*]: 4
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sdc data_in[0]: dir=input
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sdc data_in[1]: dir=input
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sdc data_in[2]: dir=input
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sdc data_in[3]: dir=input
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sdc flat pins: 44
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sdc hier pins: 44
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sdc n* nets: 8
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sdc hier nets: 19
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sdc buf* cells: 4
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sdc and* cells: 4
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sdc reg* cells: 4
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sdc hier cells: 12
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Startpoint: data_in[0] (input port clocked by clk)
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Endpoint: reg0 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v data_in[0] (in)
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0.06 0.06 v buf0/Z (BUF_X1)
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0.03 0.08 v and0/ZN (AND2_X1)
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0.00 0.08 v reg0/D (DFF_X1)
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0.08 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg0/CK (DFF_X1)
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-0.04 9.96 library setup time
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9.96 data required time
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---------------------------------------------------------
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9.96 data required time
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-0.08 data arrival time
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---------------------------------------------------------
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9.88 slack (MET)
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Startpoint: enable (input port clocked by clk)
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Endpoint: reg0 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: min
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ input external delay
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0.00 0.00 ^ enable (in)
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0.04 0.04 ^ and0/ZN (AND2_X1)
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0.00 0.04 ^ reg0/D (DFF_X1)
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0.04 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 ^ reg0/CK (DFF_X1)
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0.01 0.01 library hold time
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0.01 data required time
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---------------------------------------------------------
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0.01 data required time
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-0.04 data arrival time
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---------------------------------------------------------
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0.04 slack (MET)
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sta ports: 11
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sta cells: 12
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sta nets: 19
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Startpoint: data_in[0] (input port clocked by clk)
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Endpoint: reg0 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v data_in[0] (in)
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0.06 0.06 v buf0/Z (BUF_X1)
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0.03 0.08 v and0/ZN (AND2_X1)
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0.00 0.08 v reg0/D (DFF_X1)
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0.08 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg0/CK (DFF_X1)
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-0.04 9.96 library setup time
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9.96 data required time
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---------------------------------------------------------
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9.96 data required time
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-0.08 data arrival time
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---------------------------------------------------------
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9.88 slack (MET)
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--- Test 2: SDC namespace with hierarchical design ---
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sdc hier cells: 11
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sdc hier pins: 30
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sdc hier nets: 19
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sdc sub* cells: 2
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sdc hier sub*: 2
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sdc port clk: dir=input
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sdc port in1: dir=input
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sdc port in2: dir=input
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sdc port in3: dir=input
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sdc port out1: dir=output
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sdc port out2: dir=output
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Startpoint: in1 (input port clocked by clk)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v in1 (in)
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0.06 0.06 v buf_in/Z (BUF_X1)
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0.03 0.08 v sub1/and_gate/ZN (AND2_X1)
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0.02 0.11 v sub1/buf_gate/Z (BUF_X1)
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0.02 0.13 v sub2/and_gate/ZN (AND2_X1)
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0.03 0.16 v sub2/buf_gate/Z (BUF_X1)
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0.01 0.17 ^ inv1/ZN (INV_X1)
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0.00 0.17 ^ reg1/D (DFF_X1)
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0.17 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg1/CK (DFF_X1)
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-0.03 9.97 library setup time
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9.97 data required time
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---------------------------------------------------------
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9.97 data required time
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-0.17 data arrival time
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---------------------------------------------------------
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9.80 slack (MET)
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No paths found.
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Startpoint: in1 (input port clocked by clk)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v in1 (in)
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0.06 0.06 v buf_in/Z (BUF_X1)
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0.03 0.08 v sub1/and_gate/ZN (AND2_X1)
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0.02 0.11 v sub1/buf_gate/Z (BUF_X1)
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0.02 0.13 v sub2/and_gate/ZN (AND2_X1)
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0.03 0.16 v sub2/buf_gate/Z (BUF_X1)
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0.01 0.17 ^ inv1/ZN (INV_X1)
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0.00 0.17 ^ reg1/D (DFF_X1)
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0.17 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg1/CK (DFF_X1)
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-0.03 9.97 library setup time
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9.97 data required time
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---------------------------------------------------------
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9.97 data required time
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-0.17 data arrival time
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---------------------------------------------------------
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9.80 slack (MET)
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--- Test 3: path divider ---
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sub1/* pins (default divider): 3
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hier sub1/* pins: 3
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sub1 cell ref: sub_block
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all nets: 11
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hier all nets: 19
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No paths found.
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Startpoint: in2 (input port clocked by clk)
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Endpoint: out2 (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v in2 (in)
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0.06 0.06 v sub1/and_gate/ZN (AND2_X1)
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0.02 0.09 v sub1/buf_gate/Z (BUF_X1)
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0.02 0.11 v sub2/and_gate/ZN (AND2_X1)
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0.03 0.14 v sub2/buf_gate/Z (BUF_X1)
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0.02 0.16 v buf_out2/Z (BUF_X1)
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0.00 0.16 v out2 (out)
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0.16 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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0.00 10.00 output external delay
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10.00 data required time
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---------------------------------------------------------
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10.00 data required time
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-0.16 data arrival time
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---------------------------------------------------------
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9.84 slack (MET)
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Startpoint: in3 (input port clocked by clk)
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Endpoint: out2 (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v in3 (in)
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0.06 0.06 v sub2/and_gate/ZN (AND2_X1)
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0.03 0.09 v sub2/buf_gate/Z (BUF_X1)
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0.02 0.11 v buf_out2/Z (BUF_X1)
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0.00 0.11 v out2 (out)
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0.11 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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0.00 10.00 output external delay
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10.00 data required time
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---------------------------------------------------------
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10.00 data required time
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-0.11 data arrival time
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---------------------------------------------------------
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9.89 slack (MET)
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fanin to out1 flat: 5
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fanout from in1 flat: 17
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fanin to out2 cells: 2
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fanout from in3 endpoints: 0
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--- Test 4: register queries ---
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all_registers: 1
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register data_pins: 1
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register clock_pins: 1
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register output_pins: 2
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register async_pins: 0
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