22 lines
680 B
Verilog
22 lines
680 B
Verilog
// Hierarchical design for testing hierarchical network traversal,
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// HpinDrvrLoad, and SdcNetwork functions.
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module sub_block (input A, input B, output Y);
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wire n1;
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AND2_X1 and_gate (.A1(A), .A2(B), .ZN(n1));
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BUF_X1 buf_gate (.A(n1), .Z(Y));
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endmodule
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module network_hier_test (clk, in1, in2, in3, out1, out2);
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input clk, in1, in2, in3;
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output out1, out2;
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wire w1, w2, w3, w4, w5;
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BUF_X1 buf_in (.A(in1), .Z(w1));
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sub_block sub1 (.A(w1), .B(in2), .Y(w2));
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sub_block sub2 (.A(w2), .B(in3), .Y(w3));
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INV_X1 inv1 (.A(w3), .ZN(w4));
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DFF_X1 reg1 (.D(w4), .CK(clk), .Q(w5));
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BUF_X2 buf_out1 (.A(w5), .Z(out1));
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BUF_X1 buf_out2 (.A(w3), .Z(out2));
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endmodule
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