142 lines
4.5 KiB
C++
142 lines
4.5 KiB
C++
// OpenSTA, Static Timing Analyzer
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// Copyright (c) 2025, Parallax Software, Inc.
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <https://www.gnu.org/licenses/>.
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//
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// The origin of this software must not be misrepresented; you must not
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// claim that you wrote the original software.
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//
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// Altered source versions must be plainly marked as such, and must not be
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// misrepresented as being the original software.
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//
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// This notice may not be removed or altered from any source distribution.
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#pragma once
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#include "Map.hh"
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#include "Transition.hh"
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#include "NetworkClass.hh"
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#include "Graph.hh"
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#include "SdcClass.hh"
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#include "SearchClass.hh"
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#include "StaState.hh"
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namespace sta {
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class GenclkInfo;
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class BfsFwdIterator;
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class BfsBkwdIterator;
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class SearchPred;
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class TagGroupBldr;
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typedef std::pair<const Clock*,const Pin *> ClockPinPair;
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class ClockPinPairLess
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{
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public:
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bool operator()(const ClockPinPair &pair1,
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const ClockPinPair &pair2) const;
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};
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typedef Map<Clock*, GenclkInfo*> GenclkInfoMap;
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typedef Map<ClockPinPair, std::vector<Path>, ClockPinPairLess> GenclkSrcPathMap;
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typedef std::map<Vertex*, std::vector<const Path*>, VertexIdLess> VertexGenclkSrcPathsMap;
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class Genclks : public StaState
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{
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public:
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Genclks(StaState *sta);
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~Genclks();
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void clear();
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void ensureInsertionDelays();
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VertexSet *fanins(const Clock *clk);
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void findLatchFdbkEdges(const Clock *clk);
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EdgeSet *latchFdbkEdges(const Clock *clk);
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void checkMaster(Clock *gclk);
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void ensureMaster(Clock *gclk);
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// Generated clock insertion delay.
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Arrival insertionDelay(const Clock *clk,
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const Pin *pin,
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const RiseFall *rf,
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const EarlyLate *early_late,
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const PathAnalysisPt *path_ap) const;
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// Generated clock source path for a clock path root.
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const Path *srcPath(const Path *clk_path) const;
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// Generated clock source path.
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const Path *srcPath(const ClockEdge *clk_edge,
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const Pin *src_pin,
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const PathAnalysisPt *path_ap) const;
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const Path *srcPath(const Clock *clk,
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const Pin *src_pin,
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const RiseFall *rf,
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const PathAnalysisPt *path_ap) const;
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Vertex *srcPath(const Pin *pin) const;
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Level clkPinMaxLevel(const Clock *clk) const;
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void copyGenClkSrcPaths(Vertex *vertex,
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TagGroupBldr *tag_bldr);
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private:
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void findInsertionDelays();
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GenclkInfo *genclkInfo(const Clock *gclk) const;
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void clearSrcPaths();
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void recordSrcPaths(Clock *gclk);
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void findInsertionDelays(Clock *gclk);
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void seedClkVertices(Clock *clk,
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BfsBkwdIterator &iter,
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VertexSet *fanins);
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size_t srcPathIndex(const RiseFall *clk_rf,
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const PathAnalysisPt *path_ap) const;
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bool matchesSrcFilter(Path *path,
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const Clock *gclk) const;
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void seedSrcPins(Clock *gclk,
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FilterPath *src_filter,
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BfsFwdIterator &insert_iter);
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void findSrcArrivals(Clock *gclk,
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BfsFwdIterator &insert_iter,
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GenclkInfo *genclk_info);
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virtual FilterPath *makeSrcFilter(Clock *gclk);
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void deleteGenClkInfo();
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virtual Tag *makeTag(const Clock *gclk,
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const Clock *master_clk,
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const Pin *master_pin,
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const RiseFall *rf,
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FilterPath *src_filter,
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Arrival insert,
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const PathAnalysisPt *path_ap);
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void seedSrcPins(Clock *clk,
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BfsBkwdIterator &iter);
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void findInsertionDelay(Clock *gclk);
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GenclkInfo *makeGenclkInfo(Clock *gclk);
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FilterPath *srcFilter(Clock *gclk);
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void findFanin(Clock *gclk,
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// Return value.
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VertexSet *fanins);
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void findLatchFdbkEdges(const Clock *clk,
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GenclkInfo *genclk_info);
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void findLatchFdbkEdges(Vertex *vertex,
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Level gclk_level,
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SearchPred &srch_pred,
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VertexSet &path_vertices,
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VertexSet &visited_vertices,
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EdgeSet *&fdbk_edges);
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void deleteGenclkSrcPaths(Clock *gclk);
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bool found_insertion_delays_;
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GenclkSrcPathMap genclk_src_paths_;
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GenclkInfoMap genclk_info_map_;
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VertexGenclkSrcPathsMap vertex_src_paths_map_;
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};
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} // namespace
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