195 lines
5.6 KiB
Plaintext
195 lines
5.6 KiB
Plaintext
Startpoint: in1 (input port clocked by clk)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v in1 (in)
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2.03 2.03 v buf1/Z (BUF_X1)
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0.10 2.13 v and1/ZN (AND2_X1)
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0.00 2.13 v reg1/D (DFF_X1)
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2.13 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg1/CK (DFF_X1)
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-0.13 9.87 library setup time
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9.87 data required time
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---------------------------------------------------------
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9.87 data required time
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-2.13 data arrival time
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---------------------------------------------------------
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7.74 slack (MET)
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--- instance pattern matching ---
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buf1 exact: buf1
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buf* matches: 1
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and* matches: 1
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reg* matches: 1
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*1 matches: 3
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?uf1 matches: 1
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hier * cells: 3
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hier buf* cells: 1
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hier reg* cells: 1
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--- net pattern matching ---
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n1 exact: n1
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n* matches: 2
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* nets: 6
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hier n* nets: 2
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hier * nets: 6
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--- pin pattern matching ---
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buf1/* matches: 2
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*/A matches: 1
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*/Z matches: 1
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*/ZN matches: 1
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*/CK matches: 1
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*/D matches: 1
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*/Q matches: 1
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hier * pins: 11
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hier *A* pins: 3
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--- port pattern matching ---
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* ports: 4
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in* ports: 2
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out* ports: 1
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clk* ports: 1
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input ports: 3
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output ports: 1
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--- cell filter expressions ---
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ref_name==BUF_X1: 1
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ref_name==AND2_X1: 1
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ref_name==DFF_X1: 1
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ref_name=~*X1: 3
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--- collection queries ---
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all_inputs: 3
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all_outputs: 1
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all_clocks: 1
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all_registers: 1
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register data_pins: 1
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register clock_pins: 1
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register output_pins: 2
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--- lib cell pattern matching ---
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all lib cells: 134
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BUF* lib cells: 6
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AND* lib cells: 9
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DFF* lib cells: 8
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--- report_checks with patterns ---
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Startpoint: in1 (input port clocked by clk)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v in1 (in)
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2.03 2.03 v buf1/Z (BUF_X1)
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0.10 2.13 v and1/ZN (AND2_X1)
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0.00 2.13 v reg1/D (DFF_X1)
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2.13 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg1/CK (DFF_X1)
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-0.13 9.87 library setup time
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9.87 data required time
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---------------------------------------------------------
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9.87 data required time
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-2.13 data arrival time
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---------------------------------------------------------
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7.74 slack (MET)
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Startpoint: in2 (input port clocked by clk)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v in2 (in)
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2.13 2.13 v and1/ZN (AND2_X1)
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0.00 2.13 v reg1/D (DFF_X1)
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2.13 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg1/CK (DFF_X1)
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-0.13 9.87 library setup time
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9.87 data required time
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---------------------------------------------------------
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9.87 data required time
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-2.13 data arrival time
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---------------------------------------------------------
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7.74 slack (MET)
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: out1 (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg1/CK (DFF_X1)
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0.08 0.08 ^ reg1/Q (DFF_X1)
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0.00 0.08 ^ out1 (out)
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0.08 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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0.00 10.00 output external delay
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10.00 data required time
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---------------------------------------------------------
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10.00 data required time
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-0.08 data arrival time
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---------------------------------------------------------
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9.92 slack (MET)
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No paths found.
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Startpoint: in1 (input port clocked by clk)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v in1 (in)
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2.03 2.03 v buf1/Z (BUF_X1)
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0.10 2.13 v and1/ZN (AND2_X1)
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0.00 2.13 v reg1/D (DFF_X1)
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2.13 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg1/CK (DFF_X1)
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-0.13 9.87 library setup time
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9.87 data required time
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---------------------------------------------------------
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9.87 data required time
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-2.13 data arrival time
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---------------------------------------------------------
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7.74 slack (MET)
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