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OpenSTA/network/test/network_leaf_iter.ok

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Startpoint: in1 (input port clocked by clk)
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 v input external delay
0.00 0.00 v in1 (in)
0.06 0.06 v buf_in/Z (BUF_X1)
0.03 0.08 v sub1/and_gate/ZN (AND2_X1)
0.02 0.11 v sub1/buf_gate/Z (BUF_X1)
0.02 0.13 v sub2/and_gate/ZN (AND2_X1)
0.03 0.16 v sub2/buf_gate/Z (BUF_X1)
0.01 0.17 ^ inv1/ZN (INV_X1)
0.00 0.17 ^ reg1/D (DFF_X1)
0.17 data arrival time
10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
10.00 ^ reg1/CK (DFF_X1)
-0.03 9.97 library setup time
9.97 data required time
---------------------------------------------------------
9.97 data required time
-0.17 data arrival time
---------------------------------------------------------
9.80 slack (MET)
--- leaf instance queries ---
flat cells: 7
hierarchical cells: 11
inst buf_in: ref=BUF_X1 full=buf_in
inst sub1: ref=sub_block full=sub1
inst sub2: ref=sub_block full=sub2
inst inv1: ref=INV_X1 full=inv1
inst reg1: ref=DFF_X1 full=reg1
inst buf_out1: ref=BUF_X2 full=buf_out1
inst buf_out2: ref=BUF_X1 full=buf_out2
--- path traversal ---
deep *gate* cells: 4
hier: buf_in ref=BUF_X1
hier: buf_out1 ref=BUF_X2
hier: buf_out2 ref=BUF_X1
hier: inv1 ref=INV_X1
hier: reg1 ref=DFF_X1
hier: sub1 ref=sub_block
hier: sub1/and_gate ref=AND2_X1
hier: sub1/buf_gate ref=BUF_X1
hier: sub2 ref=sub_block
hier: sub2/and_gate ref=AND2_X1
hier: sub2/buf_gate ref=BUF_X1
--- port queries ---
total ports: 6
input ports: 4
output ports: 2
port clk: dir=input name=clk
port in1: dir=input name=in1
port in2: dir=input name=in2
port in3: dir=input name=in3
port out1: dir=output name=out1
port out2: dir=output name=out2
--- pin queries ---
flat pins: 20
all hierarchical pins: 30
*/A pins: 6
*/Z pins: 3
*/ZN pins: 1
*/CK pins: 1
sub*/* hier pins: 6
sub1/* hier pins: 3
sub2/* hier pins: 3
--- net queries ---
flat nets: 11
hierarchical nets: 19
w* nets: 5
w* hier nets: 5
net w1: name=w1
net w2: name=w2
net w3: name=w3
net w4: name=w4
net w5: name=w5
--- fanin/fanout traversal ---
fanin to out1 flat: 5
fanin to out1 cells: 3
fanin to out1 startpoints: 1
fanout from in1 flat: 17
fanout from in1 cells: 2
fanout from in1 endpoints: 0
fanin to out2 flat: 18
fanout from in2 flat: 15
fanout from in3 flat: 11
fanin timing: 5
fanin all: 5
fanout timing: 17
fanout all: 17
--- timing reports ---
No paths found.
No paths found.
Startpoint: in3 (input port clocked by clk)
Endpoint: out2 (output port clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 v input external delay
0.00 0.00 v in3 (in)
0.06 0.06 v sub2/and_gate/ZN (AND2_X1)
0.03 0.09 v sub2/buf_gate/Z (BUF_X1)
0.02 0.11 v buf_out2/Z (BUF_X1)
0.00 0.11 v out2 (out)
0.11 data arrival time
10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
0.00 10.00 output external delay
10.00 data required time
---------------------------------------------------------
10.00 data required time
-0.11 data arrival time
---------------------------------------------------------
9.89 slack (MET)
Startpoint: in3 (input port clocked by clk)
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: min
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 ^ input external delay
0.00 0.00 ^ in3 (in)
0.04 0.04 ^ sub2/and_gate/ZN (AND2_X1)
0.02 0.07 ^ sub2/buf_gate/Z (BUF_X1)
0.01 0.07 v inv1/ZN (INV_X1)
0.00 0.07 v reg1/D (DFF_X1)
0.07 data arrival time
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 clock reconvergence pessimism
0.00 ^ reg1/CK (DFF_X1)
0.00 0.00 library hold time
0.00 data required time
---------------------------------------------------------
0.00 data required time
-0.07 data arrival time
---------------------------------------------------------
0.07 slack (MET)
Startpoint: in1 (input port clocked by clk)
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 v input external delay
0.00 0.00 v in1 (in)
0.06 0.06 v buf_in/Z (BUF_X1)
0.03 0.08 v sub1/and_gate/ZN (AND2_X1)
0.02 0.11 v sub1/buf_gate/Z (BUF_X1)
0.02 0.13 v sub2/and_gate/ZN (AND2_X1)
0.03 0.16 v sub2/buf_gate/Z (BUF_X1)
0.01 0.17 ^ inv1/ZN (INV_X1)
0.00 0.17 ^ reg1/D (DFF_X1)
0.17 data arrival time
10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
10.00 ^ reg1/CK (DFF_X1)
-0.03 9.97 library setup time
9.97 data required time
---------------------------------------------------------
9.97 data required time
-0.17 data arrival time
---------------------------------------------------------
9.80 slack (MET)
Warning 168: network_leaf_iter.tcl line 1, unknown field nets.
Startpoint: in1 (input port clocked by clk)
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 v input external delay
1 0.88 0.10 0.00 0.00 v in1 (in)
0.10 0.00 0.00 v buf_in/A (BUF_X1)
1 0.87 0.01 0.06 0.06 v buf_in/Z (BUF_X1)
0.01 0.00 0.06 v sub1/and_gate/A1 (AND2_X1)
1 0.88 0.01 0.03 0.08 v sub1/and_gate/ZN (AND2_X1)
0.01 0.00 0.08 v sub1/buf_gate/A (BUF_X1)
1 0.87 0.00 0.02 0.11 v sub1/buf_gate/Z (BUF_X1)
0.00 0.00 0.11 v sub2/and_gate/A1 (AND2_X1)
1 0.88 0.01 0.02 0.13 v sub2/and_gate/ZN (AND2_X1)
0.01 0.00 0.13 v sub2/buf_gate/A (BUF_X1)
2 2.42 0.01 0.03 0.16 v sub2/buf_gate/Z (BUF_X1)
0.01 0.00 0.16 v inv1/A (INV_X1)
1 1.14 0.01 0.01 0.17 ^ inv1/ZN (INV_X1)
0.01 0.00 0.17 ^ reg1/D (DFF_X1)
0.17 data arrival time
0.00 10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
10.00 ^ reg1/CK (DFF_X1)
-0.03 9.97 library setup time
9.97 data required time
-----------------------------------------------------------------------------
9.97 data required time
-0.17 data arrival time
-----------------------------------------------------------------------------
9.80 slack (MET)
Startpoint: in1 (input port clocked by clk)
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 v input external delay
0.00 0.00 v in1 (in)
0.06 0.06 v buf_in/Z (BUF_X1)
0.03 0.08 v sub1/and_gate/ZN (AND2_X1)
0.02 0.11 v sub1/buf_gate/Z (BUF_X1)
0.02 0.13 v sub2/and_gate/ZN (AND2_X1)
0.03 0.16 v sub2/buf_gate/Z (BUF_X1)
0.01 0.17 ^ inv1/ZN (INV_X1)
0.00 0.17 ^ reg1/D (DFF_X1)
0.17 data arrival time
10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
10.00 ^ reg1/CK (DFF_X1)
-0.03 9.97 library setup time
9.97 data required time
---------------------------------------------------------
9.97 data required time
-0.17 data arrival time
---------------------------------------------------------
9.80 slack (MET)
Startpoint: in1 (input port clocked by clk)
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 v input external delay
0.00 0.00 v in1 (in)
0.06 0.06 v buf_in/Z (BUF_X1)
0.03 0.08 v sub1/and_gate/ZN (AND2_X1)
0.02 0.11 v sub1/buf_gate/Z (BUF_X1)
0.02 0.13 v sub2/and_gate/ZN (AND2_X1)
0.03 0.16 v sub2/buf_gate/Z (BUF_X1)
0.01 0.17 ^ inv1/ZN (INV_X1)
0.00 0.17 ^ reg1/D (DFF_X1)
0.17 data arrival time
10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
10.00 ^ reg1/CK (DFF_X1)
-0.03 9.97 library setup time
9.97 data required time
---------------------------------------------------------
9.97 data required time
-0.17 data arrival time
---------------------------------------------------------
9.80 slack (MET)
Warning 502: network_leaf_iter.tcl line 1, report_checks -endpoint_count is deprecated. Use -endpoint_path_count instead.
Startpoint: in1 (input port clocked by clk)
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 v input external delay
0.00 0.00 v in1 (in)
0.06 0.06 v buf_in/Z (BUF_X1)
0.03 0.08 v sub1/and_gate/ZN (AND2_X1)
0.02 0.11 v sub1/buf_gate/Z (BUF_X1)
0.02 0.13 v sub2/and_gate/ZN (AND2_X1)
0.03 0.16 v sub2/buf_gate/Z (BUF_X1)
0.01 0.17 ^ inv1/ZN (INV_X1)
0.00 0.17 ^ reg1/D (DFF_X1)
0.17 data arrival time
10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
10.00 ^ reg1/CK (DFF_X1)
-0.03 9.97 library setup time
9.97 data required time
---------------------------------------------------------
9.97 data required time
-0.17 data arrival time
---------------------------------------------------------
9.80 slack (MET)
Startpoint: in1 (input port clocked by clk)
Endpoint: out2 (output port clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 v input external delay
0.00 0.00 v in1 (in)
0.06 0.06 v buf_in/Z (BUF_X1)
0.03 0.08 v sub1/and_gate/ZN (AND2_X1)
0.02 0.11 v sub1/buf_gate/Z (BUF_X1)
0.02 0.13 v sub2/and_gate/ZN (AND2_X1)
0.03 0.16 v sub2/buf_gate/Z (BUF_X1)
0.02 0.18 v buf_out2/Z (BUF_X1)
0.00 0.18 v out2 (out)
0.18 data arrival time
10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
0.00 10.00 output external delay
10.00 data required time
---------------------------------------------------------
10.00 data required time
-0.18 data arrival time
---------------------------------------------------------
9.82 slack (MET)
Startpoint: in2 (input port clocked by clk)
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 v input external delay
0.00 0.00 v in2 (in)
0.06 0.06 v sub1/and_gate/ZN (AND2_X1)
0.02 0.09 v sub1/buf_gate/Z (BUF_X1)
0.02 0.11 v sub2/and_gate/ZN (AND2_X1)
0.03 0.14 v sub2/buf_gate/Z (BUF_X1)
0.01 0.15 ^ inv1/ZN (INV_X1)
0.00 0.15 ^ reg1/D (DFF_X1)
0.15 data arrival time
10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
10.00 ^ reg1/CK (DFF_X1)
-0.03 9.97 library setup time
9.97 data required time
---------------------------------------------------------
9.97 data required time
-0.15 data arrival time
---------------------------------------------------------
9.82 slack (MET)
Warning 503: network_leaf_iter.tcl line 1, report_checks -group_count is deprecated. Use -group_path_count instead.
Startpoint: in1 (input port clocked by clk)
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 v input external delay
0.00 0.00 v in1 (in)
0.06 0.06 v buf_in/Z (BUF_X1)
0.03 0.08 v sub1/and_gate/ZN (AND2_X1)
0.02 0.11 v sub1/buf_gate/Z (BUF_X1)
0.02 0.13 v sub2/and_gate/ZN (AND2_X1)
0.03 0.16 v sub2/buf_gate/Z (BUF_X1)
0.01 0.17 ^ inv1/ZN (INV_X1)
0.00 0.17 ^ reg1/D (DFF_X1)
0.17 data arrival time
10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
10.00 ^ reg1/CK (DFF_X1)
-0.03 9.97 library setup time
9.97 data required time
---------------------------------------------------------
9.97 data required time
-0.17 data arrival time
---------------------------------------------------------
9.80 slack (MET)
Startpoint: in1 (input port clocked by clk)
Endpoint: out2 (output port clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 v input external delay
0.00 0.00 v in1 (in)
0.06 0.06 v buf_in/Z (BUF_X1)
0.03 0.08 v sub1/and_gate/ZN (AND2_X1)
0.02 0.11 v sub1/buf_gate/Z (BUF_X1)
0.02 0.13 v sub2/and_gate/ZN (AND2_X1)
0.03 0.16 v sub2/buf_gate/Z (BUF_X1)
0.02 0.18 v buf_out2/Z (BUF_X1)
0.00 0.18 v out2 (out)
0.18 data arrival time
10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
0.00 10.00 output external delay
10.00 data required time
---------------------------------------------------------
10.00 data required time
-0.18 data arrival time
---------------------------------------------------------
9.82 slack (MET)
--- network modify in hierarchy ---
--- register queries ---
all_registers: 1
data_pins: 1
clock_pins: 1
output_pins: 2
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