1040 lines
34 KiB
Plaintext
1040 lines
34 KiB
Plaintext
--- baseline report_checks ---
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Startpoint: d1 (input port clocked by clk)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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1.00 1.00 ^ input external delay
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0.00 1.00 ^ d1 (in)
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0.03 1.03 ^ buf1/Z (BUF_X1)
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0.01 1.04 v inv1/ZN (INV_X1)
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0.03 1.07 v and1/ZN (AND2_X1)
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0.05 1.11 v or1/ZN (OR2_X1)
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0.03 1.14 v buf3/Z (BUF_X1)
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0.00 1.14 v reg2/D (DFF_X1)
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1.14 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg2/CK (DFF_X1)
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-0.04 9.96 library setup time
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9.96 data required time
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---------------------------------------------------------
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9.96 data required time
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-1.14 data arrival time
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---------------------------------------------------------
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8.82 slack (MET)
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Startpoint: en (input port clocked by clk)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: min
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ input external delay
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0.00 0.00 ^ en (in)
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0.05 0.05 ^ and1/ZN (AND2_X1)
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0.00 0.05 ^ reg1/D (DFF_X1)
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0.05 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 ^ reg1/CK (DFF_X1)
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0.01 0.01 library hold time
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0.01 data required time
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---------------------------------------------------------
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0.01 data required time
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-0.05 data arrival time
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---------------------------------------------------------
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0.04 slack (MET)
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Startpoint: d1 (input port clocked by clk)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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1.00 1.00 ^ input external delay
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0.00 1.00 ^ d1 (in)
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0.03 1.03 ^ buf1/Z (BUF_X1)
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0.01 1.04 v inv1/ZN (INV_X1)
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0.03 1.07 v and1/ZN (AND2_X1)
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0.05 1.11 v or1/ZN (OR2_X1)
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0.03 1.14 v buf3/Z (BUF_X1)
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0.00 1.14 v reg2/D (DFF_X1)
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1.14 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg2/CK (DFF_X1)
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-0.04 9.96 library setup time
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9.96 data required time
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---------------------------------------------------------
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9.96 data required time
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-1.14 data arrival time
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---------------------------------------------------------
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8.82 slack (MET)
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--- multiple paths ---
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No paths found.
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No paths found.
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No paths found.
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No paths found.
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No paths found.
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--- through paths ---
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Startpoint: d1 (input port clocked by clk)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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1.00 1.00 ^ input external delay
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0.00 1.00 ^ d1 (in)
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0.03 1.03 ^ buf1/Z (BUF_X1)
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0.01 1.04 v inv1/ZN (INV_X1)
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0.03 1.07 v and1/ZN (AND2_X1)
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0.05 1.11 v or1/ZN (OR2_X1)
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0.03 1.14 v buf3/Z (BUF_X1)
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0.00 1.14 v reg2/D (DFF_X1)
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1.14 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg2/CK (DFF_X1)
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-0.04 9.96 library setup time
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9.96 data required time
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---------------------------------------------------------
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9.96 data required time
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-1.14 data arrival time
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---------------------------------------------------------
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8.82 slack (MET)
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through inv1/ZN: done
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Startpoint: d1 (input port clocked by clk)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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1.00 1.00 ^ input external delay
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0.00 1.00 ^ d1 (in)
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0.03 1.03 ^ buf1/Z (BUF_X1)
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0.01 1.04 v inv1/ZN (INV_X1)
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0.03 1.07 v and1/ZN (AND2_X1)
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0.05 1.11 v or1/ZN (OR2_X1)
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0.03 1.14 v buf3/Z (BUF_X1)
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0.00 1.14 v reg2/D (DFF_X1)
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1.14 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg2/CK (DFF_X1)
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-0.04 9.96 library setup time
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9.96 data required time
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---------------------------------------------------------
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9.96 data required time
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-1.14 data arrival time
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---------------------------------------------------------
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8.82 slack (MET)
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through and1/ZN: done
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Startpoint: d1 (input port clocked by clk)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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1.00 1.00 ^ input external delay
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0.00 1.00 ^ d1 (in)
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0.03 1.03 ^ buf1/Z (BUF_X1)
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0.01 1.04 v inv1/ZN (INV_X1)
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0.03 1.07 v and1/ZN (AND2_X1)
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0.05 1.11 v or1/ZN (OR2_X1)
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0.03 1.14 v buf3/Z (BUF_X1)
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0.00 1.14 v reg2/D (DFF_X1)
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1.14 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg2/CK (DFF_X1)
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-0.04 9.96 library setup time
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9.96 data required time
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---------------------------------------------------------
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9.96 data required time
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-1.14 data arrival time
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---------------------------------------------------------
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8.82 slack (MET)
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through or1/ZN: done
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Startpoint: d1 (input port clocked by clk)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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1.00 1.00 ^ input external delay
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0.00 1.00 ^ d1 (in)
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0.03 1.03 ^ buf1/Z (BUF_X1)
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0.01 1.04 v inv1/ZN (INV_X1)
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0.03 1.07 v and1/ZN (AND2_X1)
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0.05 1.11 v or1/ZN (OR2_X1)
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0.03 1.14 v buf3/Z (BUF_X1)
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0.00 1.14 v reg2/D (DFF_X1)
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1.14 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg2/CK (DFF_X1)
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-0.04 9.96 library setup time
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9.96 data required time
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---------------------------------------------------------
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9.96 data required time
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-1.14 data arrival time
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---------------------------------------------------------
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8.82 slack (MET)
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through buf3/Z: done
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--- timing edges for multi-input cells ---
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and1 edges: 1
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or1 edges: 1
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reg1 edges: 1
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reg2 edges: 1
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and1 A1->ZN edges: 1
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and1 A2->ZN edges: 1
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or1 A1->ZN edges: 1
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--- report_edges ---
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A -> Z combinational
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^ -> ^ 0.03:0.03
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v -> v 0.06:0.06
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A -> ZN combinational
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^ -> v 0.01:0.01
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v -> ^ 0.01:0.01
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A1 -> ZN combinational
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^ -> ^ 0.03:0.03
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v -> v 0.03:0.03
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A2 -> ZN combinational
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^ -> ^ 0.05:0.05
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v -> v 0.07:0.07
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A1 -> ZN combinational
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^ -> ^ 0.03:0.03
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v -> v 0.03:0.03
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d1 -> buf1/A wire
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^ -> ^ 0.00:0.00
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v -> v 0.00:0.00
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reg2/Q -> q2 wire
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^ -> ^ 0.00:0.00
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v -> v 0.00:0.00
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--- set_case_analysis ---
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Startpoint: d1 (input port clocked by clk)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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1.00 1.00 ^ input external delay
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0.00 1.00 ^ d1 (in)
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0.03 1.03 ^ buf1/Z (BUF_X1)
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0.01 1.04 v inv1/ZN (INV_X1)
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0.03 1.07 v and1/ZN (AND2_X1)
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0.05 1.11 v or1/ZN (OR2_X1)
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0.03 1.14 v buf3/Z (BUF_X1)
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0.00 1.14 v reg2/D (DFF_X1)
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1.14 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg2/CK (DFF_X1)
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-0.04 9.96 library setup time
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9.96 data required time
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---------------------------------------------------------
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9.96 data required time
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-1.14 data arrival time
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---------------------------------------------------------
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8.82 slack (MET)
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No paths found.
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Startpoint: d2 (input port clocked by clk)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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1.00 1.00 v input external delay
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0.00 1.00 v d2 (in)
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0.05 1.05 v buf2/Z (BUF_X2)
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0.04 1.09 v or1/ZN (OR2_X1)
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0.03 1.12 v buf3/Z (BUF_X1)
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0.00 1.12 v reg2/D (DFF_X1)
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1.12 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg2/CK (DFF_X1)
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-0.04 9.96 library setup time
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9.96 data required time
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---------------------------------------------------------
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9.96 data required time
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-1.12 data arrival time
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---------------------------------------------------------
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8.84 slack (MET)
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Startpoint: d1 (input port clocked by clk)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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1.00 1.00 ^ input external delay
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0.00 1.00 ^ d1 (in)
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0.03 1.03 ^ buf1/Z (BUF_X1)
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0.01 1.04 v inv1/ZN (INV_X1)
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0.03 1.07 v and1/ZN (AND2_X1)
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0.05 1.11 v or1/ZN (OR2_X1)
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0.03 1.14 v buf3/Z (BUF_X1)
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0.00 1.14 v reg2/D (DFF_X1)
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1.14 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg2/CK (DFF_X1)
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-0.04 9.96 library setup time
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9.96 data required time
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---------------------------------------------------------
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9.96 data required time
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-1.14 data arrival time
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---------------------------------------------------------
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8.82 slack (MET)
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--- disable/enable timing multiple cells ---
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Startpoint: d2 (input port clocked by clk)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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1.00 1.00 v input external delay
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0.00 1.00 v d2 (in)
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0.05 1.05 v buf2/Z (BUF_X2)
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0.04 1.09 v or1/ZN (OR2_X1)
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0.03 1.12 v buf3/Z (BUF_X1)
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0.00 1.12 v reg2/D (DFF_X1)
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1.12 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg2/CK (DFF_X1)
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-0.04 9.96 library setup time
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9.96 data required time
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---------------------------------------------------------
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9.96 data required time
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-1.12 data arrival time
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---------------------------------------------------------
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8.84 slack (MET)
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Startpoint: d2 (input port clocked by clk)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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1.00 1.00 v input external delay
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0.00 1.00 v d2 (in)
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0.05 1.05 v buf2/Z (BUF_X2)
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0.04 1.09 v or1/ZN (OR2_X1)
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0.03 1.12 v buf3/Z (BUF_X1)
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0.00 1.12 v reg2/D (DFF_X1)
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1.12 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg2/CK (DFF_X1)
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-0.04 9.96 library setup time
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9.96 data required time
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---------------------------------------------------------
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9.96 data required time
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-1.12 data arrival time
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---------------------------------------------------------
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8.84 slack (MET)
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Startpoint: d2 (input port clocked by clk)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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1.00 1.00 v input external delay
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0.00 1.00 v d2 (in)
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0.05 1.05 v buf2/Z (BUF_X2)
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0.04 1.09 v or1/ZN (OR2_X1)
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0.03 1.12 v buf3/Z (BUF_X1)
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0.00 1.12 v reg2/D (DFF_X1)
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1.12 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg2/CK (DFF_X1)
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-0.04 9.96 library setup time
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9.96 data required time
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---------------------------------------------------------
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9.96 data required time
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-1.12 data arrival time
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---------------------------------------------------------
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8.84 slack (MET)
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Startpoint: d1 (input port clocked by clk)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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1.00 1.00 ^ input external delay
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0.00 1.00 ^ d1 (in)
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0.03 1.03 ^ buf1/Z (BUF_X1)
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0.01 1.04 v inv1/ZN (INV_X1)
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0.03 1.07 v and1/ZN (AND2_X1)
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0.05 1.11 v or1/ZN (OR2_X1)
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0.03 1.14 v buf3/Z (BUF_X1)
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0.00 1.14 v reg2/D (DFF_X1)
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1.14 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg2/CK (DFF_X1)
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-0.04 9.96 library setup time
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9.96 data required time
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---------------------------------------------------------
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9.96 data required time
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-1.14 data arrival time
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---------------------------------------------------------
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8.82 slack (MET)
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buf1 A Z constraint
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buf3 A Z constraint
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: q1 (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 ^ reg1/CK (DFF_X1)
|
|
0.08 0.08 ^ reg1/Q (DFF_X1)
|
|
0.00 0.08 ^ q1 (out)
|
|
0.08 data arrival time
|
|
|
|
10.00 10.00 clock clk (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
-1.00 9.00 output external delay
|
|
9.00 data required time
|
|
---------------------------------------------------------
|
|
9.00 data required time
|
|
-0.08 data arrival time
|
|
---------------------------------------------------------
|
|
8.92 slack (MET)
|
|
|
|
|
|
Startpoint: d1 (input port clocked by clk)
|
|
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
|
Path Group: clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
1.00 1.00 ^ input external delay
|
|
0.00 1.00 ^ d1 (in)
|
|
0.03 1.03 ^ buf1/Z (BUF_X1)
|
|
0.01 1.04 v inv1/ZN (INV_X1)
|
|
0.03 1.07 v and1/ZN (AND2_X1)
|
|
0.05 1.11 v or1/ZN (OR2_X1)
|
|
0.03 1.14 v buf3/Z (BUF_X1)
|
|
0.00 1.14 v reg2/D (DFF_X1)
|
|
1.14 data arrival time
|
|
|
|
10.00 10.00 clock clk (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
10.00 ^ reg2/CK (DFF_X1)
|
|
-0.04 9.96 library setup time
|
|
9.96 data required time
|
|
---------------------------------------------------------
|
|
9.96 data required time
|
|
-1.14 data arrival time
|
|
---------------------------------------------------------
|
|
8.82 slack (MET)
|
|
|
|
|
|
--- report_check_types ---
|
|
Startpoint: d1 (input port clocked by clk)
|
|
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
|
Path Group: clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
1.00 1.00 ^ input external delay
|
|
0.00 1.00 ^ d1 (in)
|
|
0.03 1.03 ^ buf1/Z (BUF_X1)
|
|
0.01 1.04 v inv1/ZN (INV_X1)
|
|
0.03 1.07 v and1/ZN (AND2_X1)
|
|
0.05 1.11 v or1/ZN (OR2_X1)
|
|
0.03 1.14 v buf3/Z (BUF_X1)
|
|
0.00 1.14 v reg2/D (DFF_X1)
|
|
1.14 data arrival time
|
|
|
|
10.00 10.00 clock clk (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
10.00 ^ reg2/CK (DFF_X1)
|
|
-0.04 9.96 library setup time
|
|
9.96 data required time
|
|
---------------------------------------------------------
|
|
9.96 data required time
|
|
-1.14 data arrival time
|
|
---------------------------------------------------------
|
|
8.82 slack (MET)
|
|
|
|
|
|
Startpoint: en (input port clocked by clk)
|
|
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
|
Path Group: clk
|
|
Path Type: min
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 ^ input external delay
|
|
0.00 0.00 ^ en (in)
|
|
0.05 0.05 ^ and1/ZN (AND2_X1)
|
|
0.00 0.05 ^ reg1/D (DFF_X1)
|
|
0.05 data arrival time
|
|
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 clock reconvergence pessimism
|
|
0.00 ^ reg1/CK (DFF_X1)
|
|
0.01 0.01 library hold time
|
|
0.01 data required time
|
|
---------------------------------------------------------
|
|
0.01 data required time
|
|
-0.05 data arrival time
|
|
---------------------------------------------------------
|
|
0.04 slack (MET)
|
|
|
|
|
|
Startpoint: en (input port clocked by clk)
|
|
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
|
Path Group: clk
|
|
Path Type: min
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 ^ input external delay
|
|
0.00 0.00 ^ en (in)
|
|
0.05 0.05 ^ and1/ZN (AND2_X1)
|
|
0.00 0.05 ^ reg1/D (DFF_X1)
|
|
0.05 data arrival time
|
|
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 clock reconvergence pessimism
|
|
0.00 ^ reg1/CK (DFF_X1)
|
|
0.01 0.01 library hold time
|
|
0.01 data required time
|
|
---------------------------------------------------------
|
|
0.01 data required time
|
|
-0.05 data arrival time
|
|
---------------------------------------------------------
|
|
0.04 slack (MET)
|
|
|
|
|
|
Startpoint: d1 (input port clocked by clk)
|
|
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
|
Path Group: clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
1.00 1.00 ^ input external delay
|
|
0.00 1.00 ^ d1 (in)
|
|
0.03 1.03 ^ buf1/Z (BUF_X1)
|
|
0.01 1.04 v inv1/ZN (INV_X1)
|
|
0.03 1.07 v and1/ZN (AND2_X1)
|
|
0.05 1.11 v or1/ZN (OR2_X1)
|
|
0.03 1.14 v buf3/Z (BUF_X1)
|
|
0.00 1.14 v reg2/D (DFF_X1)
|
|
1.14 data arrival time
|
|
|
|
10.00 10.00 clock clk (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
10.00 ^ reg2/CK (DFF_X1)
|
|
-0.04 9.96 library setup time
|
|
9.96 data required time
|
|
---------------------------------------------------------
|
|
9.96 data required time
|
|
-1.14 data arrival time
|
|
---------------------------------------------------------
|
|
8.82 slack (MET)
|
|
|
|
|
|
--- report_slews ---
|
|
d1 ^ 0.10:0.10 v 0.10:0.10
|
|
d2 ^ 0.10:0.10 v 0.10:0.10
|
|
en ^ 0.10:0.10 v 0.10:0.10
|
|
q1 ^ 0.01:0.01 v 0.00:0.00
|
|
q2 ^ 0.01:0.01 v 0.00:0.00
|
|
buf1/Z ^ 0.01:0.01 v 0.01:0.01
|
|
inv1/ZN ^ 0.01:0.01 v 0.00:0.00
|
|
and1/ZN ^ 0.01:0.01 v 0.01:0.01
|
|
or1/ZN ^ 0.01:0.01 v 0.01:0.01
|
|
reg1/Q ^ 0.01:0.01 v 0.00:0.00
|
|
reg2/Q ^ 0.01:0.01 v 0.00:0.00
|
|
--- report_checks -unconstrained ---
|
|
Startpoint: d1 (input port clocked by clk)
|
|
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
|
Path Group: clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
1.00 1.00 ^ input external delay
|
|
0.00 1.00 ^ d1 (in)
|
|
0.03 1.03 ^ buf1/Z (BUF_X1)
|
|
0.01 1.04 v inv1/ZN (INV_X1)
|
|
0.03 1.07 v and1/ZN (AND2_X1)
|
|
0.05 1.11 v or1/ZN (OR2_X1)
|
|
0.03 1.14 v buf3/Z (BUF_X1)
|
|
0.00 1.14 v reg2/D (DFF_X1)
|
|
1.14 data arrival time
|
|
|
|
10.00 10.00 clock clk (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
10.00 ^ reg2/CK (DFF_X1)
|
|
-0.04 9.96 library setup time
|
|
9.96 data required time
|
|
---------------------------------------------------------
|
|
9.96 data required time
|
|
-1.14 data arrival time
|
|
---------------------------------------------------------
|
|
8.82 slack (MET)
|
|
|
|
|
|
--- report_checks counts ---
|
|
Warning 503: graph_incremental.tcl line 1, report_checks -group_count is deprecated. Use -group_path_count instead.
|
|
Startpoint: d1 (input port clocked by clk)
|
|
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
|
Path Group: clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
1.00 1.00 ^ input external delay
|
|
0.00 1.00 ^ d1 (in)
|
|
0.03 1.03 ^ buf1/Z (BUF_X1)
|
|
0.01 1.04 v inv1/ZN (INV_X1)
|
|
0.03 1.07 v and1/ZN (AND2_X1)
|
|
0.05 1.11 v or1/ZN (OR2_X1)
|
|
0.03 1.14 v buf3/Z (BUF_X1)
|
|
0.00 1.14 v reg2/D (DFF_X1)
|
|
1.14 data arrival time
|
|
|
|
10.00 10.00 clock clk (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
10.00 ^ reg2/CK (DFF_X1)
|
|
-0.04 9.96 library setup time
|
|
9.96 data required time
|
|
---------------------------------------------------------
|
|
9.96 data required time
|
|
-1.14 data arrival time
|
|
---------------------------------------------------------
|
|
8.82 slack (MET)
|
|
|
|
|
|
Startpoint: d1 (input port clocked by clk)
|
|
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
|
Path Group: clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
1.00 1.00 v input external delay
|
|
0.00 1.00 v d1 (in)
|
|
0.06 1.06 v buf1/Z (BUF_X1)
|
|
0.01 1.07 ^ inv1/ZN (INV_X1)
|
|
0.03 1.10 ^ and1/ZN (AND2_X1)
|
|
0.00 1.10 ^ reg1/D (DFF_X1)
|
|
1.10 data arrival time
|
|
|
|
10.00 10.00 clock clk (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
10.00 ^ reg1/CK (DFF_X1)
|
|
-0.03 9.97 library setup time
|
|
9.97 data required time
|
|
---------------------------------------------------------
|
|
9.97 data required time
|
|
-1.10 data arrival time
|
|
---------------------------------------------------------
|
|
8.87 slack (MET)
|
|
|
|
|
|
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
|
Endpoint: q1 (output port clocked by clk)
|
|
Path Group: clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 ^ reg1/CK (DFF_X1)
|
|
0.08 0.08 ^ reg1/Q (DFF_X1)
|
|
0.00 0.08 ^ q1 (out)
|
|
0.08 data arrival time
|
|
|
|
10.00 10.00 clock clk (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
-1.00 9.00 output external delay
|
|
9.00 data required time
|
|
---------------------------------------------------------
|
|
9.00 data required time
|
|
-0.08 data arrival time
|
|
---------------------------------------------------------
|
|
8.92 slack (MET)
|
|
|
|
|
|
Warning 502: graph_incremental.tcl line 1, report_checks -endpoint_count is deprecated. Use -endpoint_path_count instead.
|
|
Startpoint: d1 (input port clocked by clk)
|
|
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
|
Path Group: clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
1.00 1.00 ^ input external delay
|
|
0.00 1.00 ^ d1 (in)
|
|
0.03 1.03 ^ buf1/Z (BUF_X1)
|
|
0.01 1.04 v inv1/ZN (INV_X1)
|
|
0.03 1.07 v and1/ZN (AND2_X1)
|
|
0.05 1.11 v or1/ZN (OR2_X1)
|
|
0.03 1.14 v buf3/Z (BUF_X1)
|
|
0.00 1.14 v reg2/D (DFF_X1)
|
|
1.14 data arrival time
|
|
|
|
10.00 10.00 clock clk (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
10.00 ^ reg2/CK (DFF_X1)
|
|
-0.04 9.96 library setup time
|
|
9.96 data required time
|
|
---------------------------------------------------------
|
|
9.96 data required time
|
|
-1.14 data arrival time
|
|
---------------------------------------------------------
|
|
8.82 slack (MET)
|
|
|
|
|
|
Startpoint: d1 (input port clocked by clk)
|
|
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
|
Path Group: clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
1.00 1.00 v input external delay
|
|
0.00 1.00 v d1 (in)
|
|
0.06 1.06 v buf1/Z (BUF_X1)
|
|
0.01 1.07 ^ inv1/ZN (INV_X1)
|
|
0.03 1.10 ^ and1/ZN (AND2_X1)
|
|
0.02 1.12 ^ or1/ZN (OR2_X1)
|
|
0.02 1.14 ^ buf3/Z (BUF_X1)
|
|
0.00 1.14 ^ reg2/D (DFF_X1)
|
|
1.14 data arrival time
|
|
|
|
10.00 10.00 clock clk (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
10.00 ^ reg2/CK (DFF_X1)
|
|
-0.03 9.97 library setup time
|
|
9.97 data required time
|
|
---------------------------------------------------------
|
|
9.97 data required time
|
|
-1.14 data arrival time
|
|
---------------------------------------------------------
|
|
8.83 slack (MET)
|
|
|
|
|
|
Startpoint: d2 (input port clocked by clk)
|
|
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
|
Path Group: clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
1.00 1.00 v input external delay
|
|
0.00 1.00 v d2 (in)
|
|
0.05 1.05 v buf2/Z (BUF_X2)
|
|
0.04 1.09 v or1/ZN (OR2_X1)
|
|
0.03 1.12 v buf3/Z (BUF_X1)
|
|
0.00 1.12 v reg2/D (DFF_X1)
|
|
1.12 data arrival time
|
|
|
|
10.00 10.00 clock clk (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
10.00 ^ reg2/CK (DFF_X1)
|
|
-0.04 9.96 library setup time
|
|
9.96 data required time
|
|
---------------------------------------------------------
|
|
9.96 data required time
|
|
-1.12 data arrival time
|
|
---------------------------------------------------------
|
|
8.84 slack (MET)
|
|
|
|
|
|
Warning 502: graph_incremental.tcl line 1, report_checks -endpoint_count is deprecated. Use -endpoint_path_count instead.
|
|
Startpoint: en (input port clocked by clk)
|
|
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
|
Path Group: clk
|
|
Path Type: min
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 ^ input external delay
|
|
0.00 0.00 ^ en (in)
|
|
0.05 0.05 ^ and1/ZN (AND2_X1)
|
|
0.00 0.05 ^ reg1/D (DFF_X1)
|
|
0.05 data arrival time
|
|
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 clock reconvergence pessimism
|
|
0.00 ^ reg1/CK (DFF_X1)
|
|
0.01 0.01 library hold time
|
|
0.01 data required time
|
|
---------------------------------------------------------
|
|
0.01 data required time
|
|
-0.05 data arrival time
|
|
---------------------------------------------------------
|
|
0.04 slack (MET)
|
|
|
|
|
|
Startpoint: en (input port clocked by clk)
|
|
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
|
Path Group: clk
|
|
Path Type: min
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 v input external delay
|
|
0.00 0.00 v en (in)
|
|
0.07 0.07 v and1/ZN (AND2_X1)
|
|
0.00 0.07 v reg1/D (DFF_X1)
|
|
0.07 data arrival time
|
|
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 clock reconvergence pessimism
|
|
0.00 ^ reg1/CK (DFF_X1)
|
|
0.00 0.00 library hold time
|
|
0.00 data required time
|
|
---------------------------------------------------------
|
|
0.00 data required time
|
|
-0.07 data arrival time
|
|
---------------------------------------------------------
|
|
0.06 slack (MET)
|
|
|
|
|
|
Startpoint: en (input port clocked by clk)
|
|
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
|
Path Group: clk
|
|
Path Type: min
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 ^ input external delay
|
|
0.00 0.00 ^ en (in)
|
|
0.05 0.05 ^ and1/ZN (AND2_X1)
|
|
0.02 0.07 ^ or1/ZN (OR2_X1)
|
|
0.02 0.09 ^ buf3/Z (BUF_X1)
|
|
0.00 0.09 ^ reg2/D (DFF_X1)
|
|
0.09 data arrival time
|
|
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 clock reconvergence pessimism
|
|
0.00 ^ reg2/CK (DFF_X1)
|
|
0.00 0.00 library hold time
|
|
0.00 data required time
|
|
---------------------------------------------------------
|
|
0.00 data required time
|
|
-0.09 data arrival time
|
|
---------------------------------------------------------
|
|
0.08 slack (MET)
|
|
|
|
|
|
Startpoint: en (input port clocked by clk)
|
|
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: min
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v en (in)
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0.07 0.07 v and1/ZN (AND2_X1)
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0.05 0.11 v or1/ZN (OR2_X1)
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0.03 0.14 v buf3/Z (BUF_X1)
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0.00 0.14 v reg2/D (DFF_X1)
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0.14 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 ^ reg2/CK (DFF_X1)
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0.00 0.00 library hold time
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0.00 data required time
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---------------------------------------------------------
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0.00 data required time
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-0.14 data arrival time
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---------------------------------------------------------
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0.14 slack (MET)
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Startpoint: d2 (input port clocked by clk)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: min
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|
|
Delay Time Description
|
|
---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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1.00 1.00 ^ input external delay
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0.00 1.00 ^ d2 (in)
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0.03 1.03 ^ buf2/Z (BUF_X2)
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0.02 1.05 ^ or1/ZN (OR2_X1)
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0.02 1.07 ^ buf3/Z (BUF_X1)
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0.00 1.07 ^ reg2/D (DFF_X1)
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1.07 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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|
0.00 0.00 clock reconvergence pessimism
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|
0.00 ^ reg2/CK (DFF_X1)
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|
0.00 0.00 library hold time
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|
0.00 data required time
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|
---------------------------------------------------------
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0.00 data required time
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|
-1.07 data arrival time
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|
---------------------------------------------------------
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1.06 slack (MET)
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