727 lines
24 KiB
Plaintext
727 lines
24 KiB
Plaintext
--- Test 1: baseline ---
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Startpoint: d2 (input port clocked by clk)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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1.00 1.00 v input external delay
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0.00 1.00 v d2 (in)
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0.06 1.06 v buf2/Z (BUF_X1)
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0.05 1.11 v or1/ZN (OR2_X1)
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0.02 1.12 ^ nand1/ZN (NAND2_X1)
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0.00 1.12 ^ reg2/D (DFF_X1)
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1.12 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg2/CK (DFF_X1)
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-0.03 9.97 library setup time
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9.97 data required time
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---------------------------------------------------------
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9.97 data required time
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-1.12 data arrival time
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---------------------------------------------------------
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8.85 slack (MET)
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Startpoint: d3 (input port clocked by clk)
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Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: min
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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1.00 1.00 ^ input external delay
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0.00 1.00 ^ d3 (in)
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0.01 1.01 v inv1/ZN (INV_X1)
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0.03 1.04 ^ nor1/ZN (NOR2_X1)
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0.00 1.04 ^ reg3/D (DFF_X1)
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1.04 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 ^ reg3/CK (DFF_X1)
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0.01 0.01 library hold time
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0.01 data required time
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---------------------------------------------------------
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0.01 data required time
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-1.04 data arrival time
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---------------------------------------------------------
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1.03 slack (MET)
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Warning 168: graph_delete_modify.tcl line 1, unknown field nets.
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Startpoint: d2 (input port clocked by clk)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Fanout Cap Slew Delay Time Description
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-----------------------------------------------------------------------------
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0.00 0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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1.00 1.00 v input external delay
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1 0.88 0.10 0.00 1.00 v d2 (in)
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0.10 0.00 1.00 v buf2/A (BUF_X1)
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2 1.69 0.01 0.06 1.06 v buf2/Z (BUF_X1)
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0.01 0.00 1.06 v or1/A1 (OR2_X1)
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2 2.56 0.01 0.05 1.11 v or1/ZN (OR2_X1)
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0.01 0.00 1.11 v nand1/A2 (NAND2_X1)
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1 1.14 0.01 0.02 1.12 ^ nand1/ZN (NAND2_X1)
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0.01 0.00 1.12 ^ reg2/D (DFF_X1)
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1.12 data arrival time
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0.00 10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg2/CK (DFF_X1)
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-0.03 9.97 library setup time
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9.97 data required time
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-----------------------------------------------------------------------------
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9.97 data required time
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-1.12 data arrival time
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-----------------------------------------------------------------------------
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8.85 slack (MET)
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--- Test 2: add/delete multiple instances ---
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Startpoint: d2 (input port clocked by clk)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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1.00 1.00 v input external delay
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0.00 1.00 v d2 (in)
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0.06 1.06 v buf2/Z (BUF_X1)
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0.05 1.11 v or1/ZN (OR2_X1)
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0.02 1.12 ^ nand1/ZN (NAND2_X1)
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0.00 1.12 ^ reg2/D (DFF_X1)
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1.12 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg2/CK (DFF_X1)
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-0.03 9.97 library setup time
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9.97 data required time
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---------------------------------------------------------
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9.97 data required time
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-1.12 data arrival time
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---------------------------------------------------------
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8.85 slack (MET)
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Startpoint: d2 (input port clocked by clk)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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1.00 1.00 v input external delay
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0.00 1.00 v d2 (in)
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0.06 1.06 v buf2/Z (BUF_X1)
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0.05 1.11 v or1/ZN (OR2_X1)
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0.02 1.12 ^ nand1/ZN (NAND2_X1)
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0.00 1.12 ^ reg2/D (DFF_X1)
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1.12 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg2/CK (DFF_X1)
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-0.03 9.97 library setup time
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9.97 data required time
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---------------------------------------------------------
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9.97 data required time
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-1.12 data arrival time
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---------------------------------------------------------
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8.85 slack (MET)
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Startpoint: d2 (input port clocked by clk)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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1.00 1.00 v input external delay
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0.00 1.00 v d2 (in)
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0.06 1.06 v buf2/Z (BUF_X1)
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0.05 1.11 v or1/ZN (OR2_X1)
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0.02 1.12 ^ nand1/ZN (NAND2_X1)
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0.00 1.12 ^ reg2/D (DFF_X1)
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1.12 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg2/CK (DFF_X1)
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-0.03 9.97 library setup time
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9.97 data required time
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---------------------------------------------------------
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9.97 data required time
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-1.12 data arrival time
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---------------------------------------------------------
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8.85 slack (MET)
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Startpoint: d2 (input port clocked by clk)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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1.00 1.00 v input external delay
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0.00 1.00 v d2 (in)
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0.06 1.06 v buf2/Z (BUF_X1)
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0.05 1.11 v or1/ZN (OR2_X1)
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0.02 1.12 ^ nand1/ZN (NAND2_X1)
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0.00 1.12 ^ reg2/D (DFF_X1)
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1.12 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg2/CK (DFF_X1)
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-0.03 9.97 library setup time
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9.97 data required time
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---------------------------------------------------------
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9.97 data required time
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-1.12 data arrival time
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---------------------------------------------------------
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8.85 slack (MET)
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--- Test 3: replace_cell ---
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Startpoint: d2 (input port clocked by clk)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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1.00 1.00 v input external delay
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0.00 1.00 v d2 (in)
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0.06 1.06 v buf2/Z (BUF_X1)
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0.05 1.11 v or1/ZN (OR2_X1)
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0.02 1.12 ^ nand1/ZN (NAND2_X1)
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0.00 1.12 ^ reg2/D (DFF_X1)
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1.12 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg2/CK (DFF_X1)
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-0.03 9.97 library setup time
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9.97 data required time
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---------------------------------------------------------
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9.97 data required time
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-1.12 data arrival time
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---------------------------------------------------------
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8.85 slack (MET)
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A -> Z combinational
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^ -> ^ 0.03:0.03
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v -> v 0.05:0.05
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Startpoint: d2 (input port clocked by clk)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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1.00 1.00 v input external delay
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0.00 1.00 v d2 (in)
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0.06 1.06 v buf2/Z (BUF_X1)
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0.05 1.11 v or1/ZN (OR2_X1)
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0.02 1.12 ^ nand1/ZN (NAND2_X1)
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0.00 1.12 ^ reg2/D (DFF_X1)
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1.12 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg2/CK (DFF_X1)
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-0.03 9.97 library setup time
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9.97 data required time
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---------------------------------------------------------
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9.97 data required time
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-1.12 data arrival time
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---------------------------------------------------------
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8.85 slack (MET)
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Startpoint: d2 (input port clocked by clk)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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1.00 1.00 v input external delay
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0.00 1.00 v d2 (in)
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0.06 1.06 v buf2/Z (BUF_X1)
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0.05 1.11 v or1/ZN (OR2_X1)
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0.02 1.12 ^ nand1/ZN (NAND2_X1)
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0.00 1.12 ^ reg2/D (DFF_X1)
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1.12 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg2/CK (DFF_X1)
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-0.03 9.97 library setup time
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9.97 data required time
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---------------------------------------------------------
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9.97 data required time
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-1.12 data arrival time
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---------------------------------------------------------
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8.85 slack (MET)
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Startpoint: d2 (input port clocked by clk)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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1.00 1.00 v input external delay
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0.00 1.00 v d2 (in)
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0.06 1.06 v buf2/Z (BUF_X1)
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0.05 1.11 v or1/ZN (OR2_X1)
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0.02 1.12 ^ nand1/ZN (NAND2_X1)
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0.00 1.12 ^ reg2/D (DFF_X1)
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1.12 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg2/CK (DFF_X1)
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-0.03 9.97 library setup time
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9.97 data required time
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---------------------------------------------------------
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9.97 data required time
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-1.12 data arrival time
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---------------------------------------------------------
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8.85 slack (MET)
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Startpoint: d2 (input port clocked by clk)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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1.00 1.00 v input external delay
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0.00 1.00 v d2 (in)
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0.06 1.06 v buf2/Z (BUF_X1)
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0.05 1.11 v or1/ZN (OR2_X1)
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0.02 1.12 ^ nand1/ZN (NAND2_X1)
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0.00 1.12 ^ reg2/D (DFF_X1)
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1.12 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg2/CK (DFF_X1)
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-0.03 9.97 library setup time
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9.97 data required time
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---------------------------------------------------------
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9.97 data required time
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-1.12 data arrival time
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---------------------------------------------------------
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8.85 slack (MET)
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Startpoint: d2 (input port clocked by clk)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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1.00 1.00 v input external delay
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0.00 1.00 v d2 (in)
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0.06 1.06 v buf2/Z (BUF_X1)
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0.05 1.11 v or1/ZN (OR2_X1)
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0.02 1.12 ^ nand1/ZN (NAND2_X1)
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0.00 1.12 ^ reg2/D (DFF_X1)
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1.12 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg2/CK (DFF_X1)
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-0.03 9.97 library setup time
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9.97 data required time
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---------------------------------------------------------
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9.97 data required time
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-1.12 data arrival time
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---------------------------------------------------------
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8.85 slack (MET)
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Startpoint: d2 (input port clocked by clk)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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1.00 1.00 v input external delay
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0.00 1.00 v d2 (in)
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0.06 1.06 v buf2/Z (BUF_X1)
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0.05 1.11 v or1/ZN (OR2_X1)
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0.02 1.12 ^ nand1/ZN (NAND2_X1)
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0.00 1.12 ^ reg2/D (DFF_X1)
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1.12 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg2/CK (DFF_X1)
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-0.03 9.97 library setup time
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9.97 data required time
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---------------------------------------------------------
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9.97 data required time
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-1.12 data arrival time
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---------------------------------------------------------
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8.85 slack (MET)
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--- Test 4: add/delete register ---
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Startpoint: d2 (input port clocked by clk)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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1.00 1.00 v input external delay
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0.00 1.00 v d2 (in)
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0.06 1.06 v buf2/Z (BUF_X1)
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0.05 1.11 v or1/ZN (OR2_X1)
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0.02 1.12 ^ nand1/ZN (NAND2_X1)
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0.00 1.12 ^ reg2/D (DFF_X1)
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1.12 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg2/CK (DFF_X1)
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-0.03 9.97 library setup time
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9.97 data required time
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---------------------------------------------------------
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9.97 data required time
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-1.12 data arrival time
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---------------------------------------------------------
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8.85 slack (MET)
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Startpoint: d2 (input port clocked by clk)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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1.00 1.00 v input external delay
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0.00 1.00 v d2 (in)
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0.06 1.06 v buf2/Z (BUF_X1)
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0.05 1.11 v or1/ZN (OR2_X1)
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0.02 1.12 ^ nand1/ZN (NAND2_X1)
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0.00 1.12 ^ reg2/D (DFF_X1)
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1.12 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg2/CK (DFF_X1)
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-0.03 9.97 library setup time
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9.97 data required time
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---------------------------------------------------------
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9.97 data required time
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-1.12 data arrival time
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---------------------------------------------------------
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8.85 slack (MET)
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--- Test 5: rapid connect/disconnect ---
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Startpoint: d2 (input port clocked by clk)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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1.00 1.00 v input external delay
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0.00 1.00 v d2 (in)
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0.06 1.06 v buf2/Z (BUF_X1)
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0.05 1.11 v or1/ZN (OR2_X1)
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0.02 1.12 ^ nand1/ZN (NAND2_X1)
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0.00 1.12 ^ reg2/D (DFF_X1)
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1.12 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg2/CK (DFF_X1)
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-0.03 9.97 library setup time
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9.97 data required time
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---------------------------------------------------------
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9.97 data required time
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-1.12 data arrival time
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---------------------------------------------------------
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8.85 slack (MET)
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cycle 1 done
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Startpoint: d2 (input port clocked by clk)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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1.00 1.00 v input external delay
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0.00 1.00 v d2 (in)
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0.06 1.06 v buf2/Z (BUF_X1)
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0.05 1.11 v or1/ZN (OR2_X1)
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0.02 1.12 ^ nand1/ZN (NAND2_X1)
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0.00 1.12 ^ reg2/D (DFF_X1)
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1.12 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg2/CK (DFF_X1)
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-0.03 9.97 library setup time
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9.97 data required time
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---------------------------------------------------------
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9.97 data required time
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-1.12 data arrival time
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---------------------------------------------------------
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8.85 slack (MET)
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cycle 2 done
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Startpoint: d2 (input port clocked by clk)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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1.00 1.00 v input external delay
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0.00 1.00 v d2 (in)
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0.06 1.06 v buf2/Z (BUF_X1)
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0.05 1.11 v or1/ZN (OR2_X1)
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0.02 1.12 ^ nand1/ZN (NAND2_X1)
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0.00 1.12 ^ reg2/D (DFF_X1)
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1.12 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg2/CK (DFF_X1)
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-0.03 9.97 library setup time
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9.97 data required time
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---------------------------------------------------------
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9.97 data required time
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-1.12 data arrival time
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---------------------------------------------------------
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8.85 slack (MET)
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cycle 3 done
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Startpoint: d2 (input port clocked by clk)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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1.00 1.00 v input external delay
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0.00 1.00 v d2 (in)
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0.06 1.06 v buf2/Z (BUF_X1)
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0.05 1.11 v or1/ZN (OR2_X1)
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0.02 1.12 ^ nand1/ZN (NAND2_X1)
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0.00 1.12 ^ reg2/D (DFF_X1)
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1.12 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg2/CK (DFF_X1)
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-0.03 9.97 library setup time
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9.97 data required time
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---------------------------------------------------------
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9.97 data required time
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-1.12 data arrival time
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---------------------------------------------------------
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8.85 slack (MET)
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--- Test 6: edge queries ---
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buf1 edges: 1
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buf2 edges: 1
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inv1 edges: 1
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and1 edges: 1
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or1 edges: 1
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nand1 edges: 1
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nor1 edges: 1
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reg1 edges: 1
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reg2 edges: 1
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reg3 edges: 1
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reg4 edges: 1
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d1 ^ 0.10:0.10 v 0.10:0.10
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d2 ^ 0.10:0.10 v 0.10:0.10
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d3 ^ 0.10:0.10 v 0.10:0.10
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buf1/Z ^ 0.01:0.01 v 0.01:0.01
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and1/ZN ^ 0.01:0.01 v 0.01:0.01
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reg1/Q ^ 0.01:0.01 v 0.00:0.00
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--- Test 7: through pins ---
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Startpoint: d2 (input port clocked by clk)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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1.00 1.00 v input external delay
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0.00 1.00 v d2 (in)
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0.06 1.06 v buf2/Z (BUF_X1)
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0.05 1.11 v or1/ZN (OR2_X1)
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0.02 1.12 ^ nand1/ZN (NAND2_X1)
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0.00 1.12 ^ reg2/D (DFF_X1)
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1.12 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg2/CK (DFF_X1)
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-0.03 9.97 library setup time
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9.97 data required time
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---------------------------------------------------------
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9.97 data required time
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-1.12 data arrival time
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---------------------------------------------------------
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8.85 slack (MET)
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through nand1: done
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Startpoint: d2 (input port clocked by clk)
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Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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1.00 1.00 v input external delay
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0.00 1.00 v d2 (in)
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0.06 1.06 v buf2/Z (BUF_X1)
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0.04 1.09 v and1/ZN (AND2_X1)
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0.02 1.11 ^ nor1/ZN (NOR2_X1)
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0.00 1.11 ^ reg3/D (DFF_X1)
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1.11 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg3/CK (DFF_X1)
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-0.03 9.97 library setup time
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9.97 data required time
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|
---------------------------------------------------------
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9.97 data required time
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-1.11 data arrival time
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---------------------------------------------------------
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8.85 slack (MET)
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through nor1: done
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Startpoint: d2 (input port clocked by clk)
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Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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1.00 1.00 v input external delay
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0.00 1.00 v d2 (in)
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0.06 1.06 v buf2/Z (BUF_X1)
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0.04 1.09 v and1/ZN (AND2_X1)
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0.02 1.11 ^ nor1/ZN (NOR2_X1)
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0.00 1.11 ^ reg3/D (DFF_X1)
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1.11 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg3/CK (DFF_X1)
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-0.03 9.97 library setup time
|
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9.97 data required time
|
|
---------------------------------------------------------
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9.97 data required time
|
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-1.11 data arrival time
|
|
---------------------------------------------------------
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8.85 slack (MET)
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through and1: done
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