54 lines
1.6 KiB
OpenEdge ABL
54 lines
1.6 KiB
OpenEdge ABL
// OpenSTA, Static Timing Analyzer
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// Copyright (c) 2025, Parallax Software, Inc.
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <https://www.gnu.org/licenses/>.
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//
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// The origin of this software must not be misrepresented; you must not
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// claim that you wrote the original software.
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//
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// Altered source versions must be plainly marked as such, and must not be
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// misrepresented as being the original software.
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//
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// This notice may not be removed or altered from any source distribution.
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%module verilog
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%{
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#include "VerilogWriter.hh"
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#include "Sta.hh"
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%}
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%inline %{
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bool
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read_verilog_cmd(const char *filename)
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{
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return Sta::sta()->readVerilog(filename);
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}
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void
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write_verilog_cmd(const char *filename,
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bool sort,
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bool include_pwr_gnd,
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CellSeq *remove_cells)
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{
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// This does NOT want the SDC (cmd) network because it wants
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// to see the sta internal names.
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Network *network = Sta::sta()->network();
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writeVerilog(filename, sort, include_pwr_gnd, remove_cells, network);
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delete remove_cells;
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}
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%} // inline
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