63 lines
1.9 KiB
Plaintext
63 lines
1.9 KiB
Plaintext
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
|
Endpoint: out1 (output port clocked by clk)
|
|
Path Group: clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 ^ reg1/CK (DFF_X1)
|
|
0.08 0.08 ^ reg1/Q (DFF_X1)
|
|
0.00 0.08 ^ out1 (out)
|
|
0.08 data arrival time
|
|
|
|
10.00 10.00 clock clk (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
0.00 10.00 output external delay
|
|
10.00 data required time
|
|
---------------------------------------------------------
|
|
10.00 data required time
|
|
-0.08 data arrival time
|
|
---------------------------------------------------------
|
|
9.92 slack (MET)
|
|
|
|
|
|
Startpoint: in1 (input port clocked by clk)
|
|
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
|
Path Group: clk
|
|
Path Type: min
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 ^ input external delay
|
|
0.00 0.00 ^ in1 (in)
|
|
0.02 0.02 ^ buf1/Z (BUF_X1)
|
|
0.01 0.02 v inv1/ZN (INV_X1)
|
|
0.00 0.02 v reg1/D (DFF_X1)
|
|
0.02 data arrival time
|
|
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 clock reconvergence pessimism
|
|
0.00 ^ reg1/CK (DFF_X1)
|
|
0.00 0.00 library hold time
|
|
0.00 data required time
|
|
---------------------------------------------------------
|
|
0.00 data required time
|
|
-0.02 data arrival time
|
|
---------------------------------------------------------
|
|
0.02 slack (MET)
|
|
|
|
|
|
time 1ns
|
|
capacitance 1fF
|
|
resistance 1kohm
|
|
voltage 1v
|
|
current 1mA
|
|
power 1nW
|
|
distance 1um
|