164 lines
5.9 KiB
Tcl
164 lines
5.9 KiB
Tcl
# Test network editing with replaceCell (equiv and non-equiv),
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# connectedCap, portExtCaps, setPortExtPinCap/WireCap/Fanout,
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# setNetWireCap, report_net, incremental timing after edits.
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# Targets: Sta.cc replaceCell, replaceEquivCellBefore/After,
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# replaceCellBefore/After, replaceCellPinInvalidate,
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# idealClockMode, libertyPortCapsEqual,
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# connectedCap (Pin and Net versions), portExtCaps,
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# setPortExtPinCap, setPortExtWireCap, setPortExtFanout,
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# setNetWireCap, removeNetLoadCaps,
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# makeInstance, deleteInstance, connectPin, disconnectPin,
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# makeNet, deleteNet, makePortPin,
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# connectPinAfter, connectDrvrPinAfter, connectLoadPinAfter,
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# disconnectPinBefore, deleteEdge, deleteNetBefore,
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# deleteInstanceBefore, deleteLeafInstanceBefore
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source ../../test/helpers.tcl
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read_liberty ../../test/nangate45/Nangate45_typ.lib
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read_verilog search_test1.v
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link_design search_test1
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create_clock -name clk -period 10 [get_ports clk]
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set_input_delay -clock clk 1.0 [get_ports in1]
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set_input_delay -clock clk 1.0 [get_ports in2]
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set_output_delay -clock clk 2.0 [get_ports out1]
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# Baseline timing
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report_checks -path_delay max > /dev/null
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############################################################
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# replaceCell with equiv cell (same ports, same timing arcs)
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# This exercises replaceEquivCellBefore/After path
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############################################################
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puts "--- replaceCell equiv: BUF_X1 -> BUF_X2 ---"
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replace_cell buf1 NangateOpenCellLibrary/BUF_X2
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report_checks -path_delay max
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puts "--- replaceCell equiv: BUF_X2 -> BUF_X4 ---"
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replace_cell buf1 NangateOpenCellLibrary/BUF_X4
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report_checks -path_delay max
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puts "--- replaceCell equiv: BUF_X4 -> BUF_X8 ---"
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replace_cell buf1 NangateOpenCellLibrary/BUF_X8
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report_checks -path_delay max
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puts "--- replaceCell back: BUF_X8 -> BUF_X1 ---"
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replace_cell buf1 NangateOpenCellLibrary/BUF_X1
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report_checks -path_delay max
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puts "--- replaceCell equiv: AND2_X1 -> AND2_X2 ---"
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replace_cell and1 NangateOpenCellLibrary/AND2_X2
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report_checks -path_delay max
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puts "--- replaceCell equiv: AND2_X2 -> AND2_X4 ---"
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replace_cell and1 NangateOpenCellLibrary/AND2_X4
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report_checks -path_delay max
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puts "--- replaceCell back: AND2_X4 -> AND2_X1 ---"
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replace_cell and1 NangateOpenCellLibrary/AND2_X1
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report_checks -path_delay max
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puts "--- replaceCell equiv buf2: BUF_X1 -> BUF_X2 ---"
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replace_cell buf2 NangateOpenCellLibrary/BUF_X2
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report_checks -path_delay max
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############################################################
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# replaceCell with propagated clock
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# This exercises idealClockMode returning false
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############################################################
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puts "--- replaceCell with propagated clock ---"
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set_propagated_clock [get_clocks clk]
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replace_cell buf1 NangateOpenCellLibrary/BUF_X2
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report_checks -path_delay max
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replace_cell buf1 NangateOpenCellLibrary/BUF_X1
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report_checks -path_delay max
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unset_propagated_clock [get_clocks clk]
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############################################################
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# Port ext pin cap, wire cap, fanout
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############################################################
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puts "--- setPortExtPinCap ---"
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set_load -pin_load 0.05 [get_ports out1]
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report_checks -path_delay max
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puts "--- setPortExtWireCap ---"
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set_load -wire_load 0.03 [get_ports out1]
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report_checks -path_delay max
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puts "--- setPortExtFanout ---"
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set_port_fanout_number 4 [get_ports out1]
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report_checks -path_delay max
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puts "--- set_load with rise/fall ---"
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set_load -pin_load 0.04 [get_ports out1]
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report_checks -path_delay max
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############################################################
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# connectedCap and report_net
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############################################################
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puts "--- report_net ---"
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report_net n1
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report_net n2
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report_net n3
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############################################################
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# setNetWireCap
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############################################################
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puts "--- setNetWireCap ---"
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set_load 0.01 [get_nets n1]
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report_checks -path_delay max
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############################################################
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# Network edits: complex sequence
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############################################################
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puts "--- Network edit: make_instance + connect + replace ---"
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make_instance new_inv1 NangateOpenCellLibrary/INV_X1
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make_net test_net1
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connect_pin test_net1 new_inv1/A
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report_checks -path_delay max
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disconnect_pin test_net1 new_inv1/A
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delete_net test_net1
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delete_instance new_inv1
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puts "--- Network edit: make multiple instances ---"
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make_instance extra_buf1 NangateOpenCellLibrary/BUF_X1
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make_instance extra_buf2 NangateOpenCellLibrary/BUF_X2
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make_instance extra_inv1 NangateOpenCellLibrary/INV_X1
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make_net extra_net1
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make_net extra_net2
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connect_pin extra_net1 extra_buf1/A
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connect_pin extra_net1 extra_buf2/A
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connect_pin extra_net2 extra_inv1/A
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report_checks -path_delay max
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disconnect_pin extra_net1 extra_buf1/A
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disconnect_pin extra_net1 extra_buf2/A
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disconnect_pin extra_net2 extra_inv1/A
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delete_net extra_net1
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delete_net extra_net2
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delete_instance extra_buf1
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delete_instance extra_buf2
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delete_instance extra_inv1
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############################################################
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# Incremental timing after replacing multiple cells
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############################################################
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puts "--- Multiple replaceCell + timing ---"
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replace_cell buf1 NangateOpenCellLibrary/BUF_X4
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replace_cell buf2 NangateOpenCellLibrary/BUF_X4
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replace_cell and1 NangateOpenCellLibrary/AND2_X4
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report_checks -path_delay max
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report_checks -path_delay min
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# Replace back
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replace_cell buf1 NangateOpenCellLibrary/BUF_X1
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replace_cell buf2 NangateOpenCellLibrary/BUF_X1
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replace_cell and1 NangateOpenCellLibrary/AND2_X1
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report_checks -path_delay max
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############################################################
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# Report timing with fields after edits
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############################################################
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puts "--- report_checks with fields after edits ---"
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report_checks -path_delay max -fields {capacitance slew fanout}
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report_checks -path_delay min -fields {capacitance slew fanout}
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