OpenSTA/verilog
dsengupta0628 9fbfcc4fcb picked changes from upstream master, resolved conflict for levelized driververtices, parseBus for weird defs
Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>
2026-04-16 21:37:37 +00:00
..
test Fix report_checks -fields {nets} typo to {net} across test scripts 2026-04-06 14:41:40 +09:00
Verilog.i clang tidy 2026-04-15 09:38:10 -07:00
Verilog.tcl update copyright 2026-03-10 14:57:45 -07:00
VerilogLex.ll string squash 2026-03-28 19:13:35 -07:00
VerilogParse.yy clang tidy 2026-04-15 09:38:10 -07:00
VerilogReader.cc clang tidy 2026-04-15 09:38:10 -07:00
VerilogReaderPvt.hh clang tidy 2026-04-15 09:38:10 -07:00
VerilogScanner.hh clang tidy 2026-04-15 09:38:10 -07:00
VerilogWriter.cc clang tidy 2026-04-15 09:38:10 -07:00