298 lines
7.7 KiB
C++
298 lines
7.7 KiB
C++
// OpenSTA, Static Timing Analyzer
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// Copyright (c) 2019, Parallax Software, Inc.
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <https://www.gnu.org/licenses/>.
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#include <stdlib.h>
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#include "Machine.hh"
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#include "Error.hh"
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#include "PortDirection.hh"
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#include "Liberty.hh"
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#include "Network.hh"
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#include "NetworkCmp.hh"
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#include "VerilogNamespace.hh"
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#include "VerilogWriter.hh"
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namespace sta {
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class VerilogWriter
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{
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public:
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VerilogWriter(const char *filename,
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bool sort,
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FILE *stream,
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Network *network);
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void writeModule(Instance *inst);
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protected:
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void writePorts(Cell *cell);
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void writePortDcls(Cell *cell);
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const char *verilogPortDir(PortDirection *dir);
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void writeChildren(Instance *inst);
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void writeChild(Instance *child);
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void writeInstPin(Instance *inst,
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Port *port,
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bool &first_port);
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void writeInstBusPin(Instance *inst,
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Port *port,
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bool &first_port);
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void writeInstBusPinBit(Instance *inst,
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Port *port,
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bool &first_member);
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const char *filename_;
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bool sort_;
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FILE *stream_;
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Network *network_;
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Set<Cell*> written_cells_;
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Set<Instance*> pending_children_;
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int unconnected_net_index_;
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};
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void
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writeVerilog(const char *filename,
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bool sort,
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Network *network)
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{
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if (network->topInstance()) {
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FILE *stream = fopen(filename, "w");
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if (stream) {
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VerilogWriter writer(filename, sort, stream, network);
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writer.writeModule(network->topInstance());
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fclose(stream);
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}
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else
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throw FileNotWritable(filename);
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}
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}
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VerilogWriter::VerilogWriter(const char *filename,
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bool sort,
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FILE *stream,
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Network *network) :
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filename_(filename),
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sort_(sort),
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stream_(stream),
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network_(network),
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unconnected_net_index_(1)
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{
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}
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void
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VerilogWriter::writeModule(Instance *inst)
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{
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Cell *cell = network_->cell(inst);
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fprintf(stream_, "module %s (",
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network_->name(cell));
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writePorts(cell);
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writePortDcls(cell);
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fprintf(stream_, "\n");
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writeChildren(inst);
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fprintf(stream_, "endmodule\n");
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written_cells_.insert(cell);
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for (auto child : pending_children_) {
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Cell *child_cell = network_->cell(child);
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if (!written_cells_.hasKey(child_cell))
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writeModule(child);
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}
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}
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void
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VerilogWriter::writePorts(Cell *cell)
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{
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bool first = true;
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CellPortIterator *port_iter = network_->portIterator(cell);
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while (port_iter->hasNext()) {
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Port *port = port_iter->next();
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if (!first)
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fprintf(stream_, ",\n ");
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fprintf(stream_, "%s", portVerilogName(network_->name(port),
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network_->pathEscape()));
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first = false;
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}
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delete port_iter;
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fprintf(stream_, ");\n");
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}
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void
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VerilogWriter::writePortDcls(Cell *cell)
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{
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CellPortIterator *port_iter = network_->portIterator(cell);
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while (port_iter->hasNext()) {
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Port *port = port_iter->next();
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PortDirection *dir = network_->direction(port);
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const char *port_name = portVerilogName(network_->name(port),
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network_->pathEscape());
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const char *vtype = verilogPortDir(dir);
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if (vtype) {
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fprintf(stream_, " %s", vtype);
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if (network_->isBus(port))
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fprintf(stream_, " [%d:%d]",
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network_->fromIndex(port),
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network_->toIndex(port));
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fprintf(stream_, " %s;\n", port_name);
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if (dir->isTristate()) {
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fprintf(stream_, " tri");
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if (network_->isBus(port))
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fprintf(stream_, " [%d:%d]",
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network_->fromIndex(port),
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network_->toIndex(port));
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fprintf(stream_, " %s;\n", port_name);
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}
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}
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}
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delete port_iter;
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}
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const char *
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VerilogWriter::verilogPortDir(PortDirection *dir)
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{
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if (dir == PortDirection::input())
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return "input";
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else if (dir == PortDirection::output())
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return "output";
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else if (dir == PortDirection::bidirect())
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return "inout";
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else if (dir == PortDirection::tristate())
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return "output";
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else
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return nullptr;
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}
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void
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VerilogWriter::writeChildren(Instance *inst)
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{
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Vector<Instance*> children;
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InstanceChildIterator *child_iter = network_->childIterator(inst);
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while (child_iter->hasNext()) {
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Instance *child = child_iter->next();
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children.push_back(child);
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if (network_->isHierarchical(child))
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pending_children_.insert(child);
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}
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delete child_iter;
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if (sort_)
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sort(children, InstancePathNameLess(network_));
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for (auto child : children)
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writeChild(child);
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}
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void
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VerilogWriter::writeChild(Instance *child)
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{
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Cell *child_cell = network_->cell(child);
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const char *child_name = network_->name(child);
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const char *child_vname = instanceVerilogName(child_name,
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network_->pathEscape());
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fprintf(stream_, " %s %s (",
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network_->name(child_cell),
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child_vname);
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bool first_port = true;
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CellPortIterator *port_iter = network_->portIterator(child_cell);
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while (port_iter->hasNext()) {
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Port *port = port_iter->next();
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if (network_->hasMembers(port))
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writeInstBusPin(child, port, first_port);
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else
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writeInstPin(child, port, first_port);
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}
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delete port_iter;
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fprintf(stream_, ");\n");
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}
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void
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VerilogWriter::writeInstPin(Instance *inst,
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Port *port,
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bool &first_port)
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{
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Pin *pin = network_->findPin(inst, port);
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if (pin) {
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Net *net = network_->net(pin);
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if (net) {
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const char *net_name = network_->name(net);
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const char *net_vname = netVerilogName(net_name, network_->pathEscape());
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if (!first_port)
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fprintf(stream_, ",\n ");
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const char *port_name = portVerilogName(network_->name(port),
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network_->pathEscape());
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fprintf(stream_, ".%s(%s)",
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port_name,
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net_vname);
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first_port = false;
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}
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}
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}
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void
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VerilogWriter::writeInstBusPin(Instance *inst,
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Port *port,
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bool &first_port)
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{
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if (!first_port)
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fprintf(stream_, ",\n ");
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fprintf(stream_, ".%s({", network_->name(port));
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first_port = false;
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bool first_member = true;
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// Match the member order of the liberty cell if it exists.
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LibertyPort *lib_port = network_->libertyPort(port);
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if (lib_port) {
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Cell *cell = network_->cell(inst);
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LibertyPortMemberIterator member_iter(lib_port);
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while (member_iter.hasNext()) {
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LibertyPort *lib_member = member_iter.next();
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Port *member = network_->findPort(cell, lib_member->name());
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writeInstBusPinBit(inst, member, first_member);
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}
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}
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else {
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PortMemberIterator *member_iter = network_->memberIterator(port);
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while (member_iter->hasNext()) {
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Port *member = member_iter->next();
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writeInstBusPinBit(inst, member, first_member);
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}
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delete member_iter;
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}
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fprintf(stream_, "})");
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}
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void
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VerilogWriter::writeInstBusPinBit(Instance *inst,
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Port *port,
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bool &first_member)
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{
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Pin *pin = network_->findPin(inst, port);
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const char *net_name = nullptr;
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if (pin) {
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Net *net = network_->net(pin);
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if (net)
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net_name = network_->name(net);
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}
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if (net_name == nullptr)
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// There is no verilog syntax to "skip" a bit in the concatentation.
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net_name = stringPrintTmp("_NC%d", unconnected_net_index_++);
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const char *net_vname = netVerilogName(net_name, network_->pathEscape());
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if (!first_member)
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fprintf(stream_, ",\n ");
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fprintf(stream_, "%s", net_vname);
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first_member = false;
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}
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} // namespace
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