188 lines
3.8 KiB
LLVM
188 lines
3.8 KiB
LLVM
%{
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// OpenSTA, Static Timing Analyzer
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// Copyright (c) 2019, Parallax Software, Inc.
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <https://www.gnu.org/licenses/>.
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#include "Machine.hh"
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#include "FlexPragma.hh"
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#include "Debug.hh"
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#include "VerilogNamespace.hh"
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#include "VerilogReaderPvt.hh"
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#include "VerilogParse.hh"
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#define YY_NO_INPUT
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int verilog_line = 1;
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static std::string string_buf;
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void
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verilogFlushBuffer()
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{
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YY_FLUSH_BUFFER;
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}
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%}
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/* %option debug */
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%option noyywrap
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%option nounput
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%option never-interactive
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%x COMMENT
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%x ATTRIBUTE
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%x QSTRING
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SIGN "+"|"-"
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UNSIGNED_NUMBER [0-9][0-9_]*
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BLANK [ \t\r]
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EOL \r?\n
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ID_ESCAPED_TOKEN \\[^ \t\r\n]+[\r\n\t ]
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ID_ALPHA_TOKEN [A-Za-z_][A-Za-z0-9_$]*
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ID_TOKEN {ID_ESCAPED_TOKEN}|{ID_ALPHA_TOKEN}
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%%
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^[ \t]*`.*{EOL} { /* Macro definition. */
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sta::verilog_reader->incrLine();
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}
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"//"[^\n]*{EOL} { /* Single line comment. */
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sta::verilog_reader->incrLine();
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}
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"/*" { BEGIN COMMENT; }
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<COMMENT>{
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.
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{EOL} { sta::verilog_reader->incrLine(); }
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"*/" { BEGIN INITIAL; }
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<<EOF>> {
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VerilogParse_error("unterminated comment");
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BEGIN(INITIAL);
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yyterminate();
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}
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}
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"(*" { BEGIN ATTRIBUTE; }
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<ATTRIBUTE>{
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.
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{EOL} { sta::verilog_reader->incrLine(); }
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"*)" { BEGIN INITIAL; }
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<<EOF>> {
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VerilogParse_error("unterminated attribute");
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BEGIN(INITIAL);
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yyterminate();
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}
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}
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{SIGN}?{UNSIGNED_NUMBER}?"'"[bB][01_xz]+ {
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VerilogParse_lval.constant = sta::stringCopy(VerilogLex_text);
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return CONSTANT;
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}
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{SIGN}?{UNSIGNED_NUMBER}?"'"[oO][0-7_xz]+ {
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VerilogParse_lval.constant = sta::stringCopy(VerilogLex_text);
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return CONSTANT;
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}
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{SIGN}?{UNSIGNED_NUMBER}?"'"[dD][0-9_]+ {
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VerilogParse_lval.constant = sta::stringCopy(VerilogLex_text);
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return CONSTANT;
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}
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{SIGN}?{UNSIGNED_NUMBER}?"'"[hH][0-9a-fA-F_xz]+ {
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VerilogParse_lval.constant = sta::stringCopy(VerilogLex_text);
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return CONSTANT;
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}
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{SIGN}?[0-9]+ {
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VerilogParse_lval.ival = atol(VerilogLex_text);
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return INT;
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}
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":"|"."|"{"|"}"|"["|"]"|","|"*"|";"|"="|"-"|"+"|"|"|"("|")" {
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return ((int) VerilogLex_text[0]);
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}
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assign { return ASSIGN; }
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endmodule { return ENDMODULE; }
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inout { return INOUT; }
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input { return INPUT; }
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module { return MODULE; }
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output { return OUTPUT; }
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parameter { return PARAMETER; }
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defparam { return DEFPARAM; }
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reg { return REG; }
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supply0 { return SUPPLY0; }
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supply1 { return SUPPLY1; }
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tri { return TRI; }
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wand { return WAND; }
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wire { return WIRE; }
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wor { return WOR; }
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{ID_TOKEN}("."{ID_TOKEN})* {
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VerilogParse_lval.string = sta::stringCopy(sta::verilogToSta(VerilogLex_text));
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return ID;
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}
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{EOL} { sta::verilog_reader->incrLine(); }
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{BLANK} { /* ignore blanks */ }
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\" {
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string_buf.erase();
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BEGIN(QSTRING);
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}
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<QSTRING>\" {
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BEGIN(INITIAL);
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VerilogParse_lval.string = sta::stringCopy(string_buf.c_str());
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return STRING;
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}
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<QSTRING>{EOL} {
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VerilogParse_error("unterminated string constant");
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BEGIN(INITIAL);
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VerilogParse_lval.string = sta::stringCopy(string_buf.c_str());
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return STRING;
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}
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<QSTRING>\\{EOL} {
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/* Line continuation. */
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sta::verilog_reader->incrLine();
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}
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<QSTRING>[^\r\n\"]+ {
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/* Anything return or double quote */
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string_buf += VerilogLex_text;
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}
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<QSTRING><<EOF>> {
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VerilogParse_error("unterminated string constant");
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BEGIN(INITIAL);
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yyterminate();
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}
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/* Send out of bound characters to parser. */
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. { return (int) VerilogLex_text[0]; }
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%%
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