60 lines
1.7 KiB
Plaintext
60 lines
1.7 KiB
Plaintext
# OpenSTA, Static Timing Analyzer
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# Copyright (c) 2018, Parallax Software, Inc.
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#
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# This program is free software: you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation, either version 3 of the License, or
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# (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program. If not, see <https://www.gnu.org/licenses/>.
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Parallax Gate Level Static Timing Analyzer
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See INSTALL for build instructions.
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Standard file formats
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Verilog
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Liberty
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SDC
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SDF
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RSPF/DSPF/SPEF
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Exception path support
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False path
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Multicycle path
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Min/Max delay
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Exception points
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-from clock/pin/instance -through pin/net -to clock/pin/instance
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Edge specific exception points
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-rise_from/-fall_from, -rise_through/-fall_through, -rise_to/-fall_to
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Clocks
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Generated
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Latency
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Source latency (insertion delay)
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Uncertainty
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Propagated/Ideal
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Gated clock checks
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Multiple frequency clocks
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Delay calculation
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Integrated Dartu/Menezes/Pileggi RC effective capacitance algorithm
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External delay calculator API
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Analysis
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Report timing checks -from, -through, -to, multiple paths to endpoint
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Report delay calculation
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Check timing setup
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Search Engine
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Query based incremental update of delays, arrival and required times
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Simulator to propagate constants from constraints and netlist tie high/low
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Timing engine library
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Network adapter uses external netlist database without duplicating any data
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