202 lines
8.4 KiB
Tcl
202 lines
8.4 KiB
Tcl
# Test Property.cc: generated clock properties (is_generated, is_virtual,
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# is_propagated, sources, period, waveform), clock pin properties (clocks,
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# clock_domains), instance and cell properties for genclk designs,
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# ReportPath.cc: reportGenClkSrcAndPath, reportGenClkSrcPath for
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# generated clock source path expansion,
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# report_checks with various formats for generated clk domain paths,
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# PathEnd properties for generated clock paths.
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# Targets: Property.cc getProperty(Clock) all branches,
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# getProperty(Pin) clocks/clock_domains,
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# ReportPath.cc reportSrcClkAndPath, reportGenClkSrcAndPath,
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# reportGenClkSrcPath, reportGenClkSrcPath1,
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# isGenPropClk, pathFromGenPropClk
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source ../../test/helpers.tcl
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read_liberty ../../test/nangate45/Nangate45_typ.lib
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read_verilog search_genclk.v
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link_design search_genclk
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create_clock -name clk -period 10 [get_ports clk]
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create_generated_clock -name div_clk -source [get_pins clkbuf/Z] -divide_by 2 [get_pins div_reg/Q]
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set_input_delay -clock clk 1.0 [get_ports in1]
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set_input_delay -clock clk 1.0 [get_ports in2]
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set_output_delay -clock clk 2.0 [get_ports out1]
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set_output_delay -clock div_clk 1.0 [get_ports out2]
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# Run timing
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report_checks -path_delay max > /dev/null
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############################################################
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# Clock properties: master vs generated
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############################################################
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puts "--- Master clock properties ---"
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set mclk [get_clocks clk]
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puts "clk name: [get_property $mclk name]"
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puts "clk full_name: [get_property $mclk full_name]"
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puts "clk period: [get_property $mclk period]"
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puts "clk is_generated: [get_property $mclk is_generated]"
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puts "clk is_virtual: [get_property $mclk is_virtual]"
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puts "clk is_propagated: [get_property $mclk is_propagated]"
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set clk_srcs [get_property $mclk sources]
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puts "clk sources: [llength $clk_srcs]"
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foreach s $clk_srcs { puts " src: [get_full_name $s]" }
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puts "--- Generated clock properties ---"
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set gclk [get_clocks div_clk]
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puts "div_clk name: [get_property $gclk name]"
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puts "div_clk full_name: [get_property $gclk full_name]"
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puts "div_clk period: [get_property $gclk period]"
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puts "div_clk is_generated: [get_property $gclk is_generated]"
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puts "div_clk is_virtual: [get_property $gclk is_virtual]"
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puts "div_clk is_propagated: [get_property $gclk is_propagated]"
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set gsrc [get_property $gclk sources]
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puts "div_clk sources: [llength $gsrc]"
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foreach s $gsrc { puts " src: [get_full_name $s]" }
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############################################################
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# Propagated clock property change
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############################################################
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puts "--- Propagated clock toggle ---"
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set_propagated_clock [get_clocks clk]
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puts "clk is_propagated (after set): [get_property [get_clocks clk] is_propagated]"
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puts "div_clk is_propagated (after set): [get_property [get_clocks div_clk] is_propagated]"
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report_checks -path_delay max > /dev/null
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unset_propagated_clock [get_clocks clk]
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puts "clk is_propagated (after unset): [get_property [get_clocks clk] is_propagated]"
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############################################################
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# Virtual clock
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############################################################
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puts "--- Virtual clock ---"
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create_clock -name vclk -period 5
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set vclk [get_clocks vclk]
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puts "vclk is_virtual: [get_property $vclk is_virtual]"
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puts "vclk is_generated: [get_property $vclk is_generated]"
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puts "vclk period: [get_property $vclk period]"
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set vsrc [get_property $vclk sources]
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puts "vclk sources: [llength $vsrc]"
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############################################################
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# Pin clocks / clock_domains
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############################################################
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puts "--- Pin clocks/clock_domains ---"
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set ck_pin_main [get_pins reg1/CK]
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set pclks [get_property $ck_pin_main clocks]
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puts "reg1/CK clocks: [llength $pclks]"
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set pdoms [get_property $ck_pin_main clock_domains]
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puts "reg1/CK clock_domains: [llength $pdoms]"
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set ck_pin_div [get_pins reg2/CK]
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set pclks2 [get_property $ck_pin_div clocks]
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puts "reg2/CK clocks: [llength $pclks2]"
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set pdoms2 [get_property $ck_pin_div clock_domains]
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puts "reg2/CK clock_domains: [llength $pdoms2]"
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set d_pin [get_pins reg1/D]
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set dclks [get_property $d_pin clocks]
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puts "reg1/D clocks: [llength $dclks]"
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set q_pin [get_pins reg1/Q]
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set qclks [get_property $q_pin clocks]
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puts "reg1/Q clocks: [llength $qclks]"
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############################################################
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# Report with generated clock paths: full_clock_expanded
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############################################################
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puts "--- GenClk full_clock_expanded max ---"
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report_checks -to [get_ports out2] -path_delay max -format full_clock_expanded -fields {capacitance slew fanout input_pin net}
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puts "--- GenClk full_clock_expanded min ---"
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report_checks -to [get_ports out2] -path_delay min -format full_clock_expanded -fields {capacitance slew fanout input_pin net}
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puts "--- GenClk full_clock max ---"
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report_checks -to [get_ports out2] -path_delay max -format full_clock -fields {capacitance slew fanout}
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puts "--- GenClk full max ---"
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report_checks -to [get_ports out2] -path_delay max -format full -fields {capacitance slew fanout}
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############################################################
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# Report genclk paths in all formats
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############################################################
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puts "--- GenClk all formats ---"
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report_checks -to [get_ports out2] -path_delay max -format short
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report_checks -to [get_ports out2] -path_delay max -format end
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report_checks -to [get_ports out2] -path_delay max -format summary
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report_checks -to [get_ports out2] -path_delay max -format slack_only
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report_checks -to [get_ports out2] -path_delay max -format json
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############################################################
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# GenClk with propagated + full_clock_expanded
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############################################################
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puts "--- GenClk propagated full_clock_expanded ---"
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set_propagated_clock [get_clocks clk]
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report_checks -to [get_ports out2] -path_delay max -format full_clock_expanded -fields {capacitance slew fanout input_pin}
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report_checks -to [get_ports out2] -path_delay min -format full_clock_expanded -fields {capacitance slew fanout input_pin}
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unset_propagated_clock [get_clocks clk]
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############################################################
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# find_timing_paths for genclk domain
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############################################################
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puts "--- find_timing_paths genclk domain ---"
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set paths_gc [find_timing_paths -to [get_ports out2] -path_delay max -endpoint_count 5]
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puts "GenClk max paths: [llength $paths_gc]"
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foreach pe $paths_gc {
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puts " pin=[get_full_name [$pe pin]] slack=[$pe slack]"
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puts " is_check: [$pe is_check] is_output: [$pe is_output_delay]"
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puts " target_clk: [get_name [$pe target_clk]]"
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puts " startpoint_clock: [get_name [get_property $pe startpoint_clock]]"
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puts " endpoint_clock: [get_name [get_property $pe endpoint_clock]]"
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set pts [get_property $pe points]
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puts " points: [llength $pts]"
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}
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############################################################
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# report_path_cmd with genclk path
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############################################################
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puts "--- report_path_cmd genclk ---"
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foreach pe $paths_gc {
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set p [$pe path]
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sta::set_report_path_format full_clock_expanded
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sta::report_path_cmd $p
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sta::set_report_path_format full
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break
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}
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############################################################
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# report_path_ends for genclk paths
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############################################################
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puts "--- report_path_ends genclk ---"
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sta::report_path_ends $paths_gc
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############################################################
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# report_clock_properties
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############################################################
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puts "--- report_clock_properties ---"
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report_clock_properties
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############################################################
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# report_clock_skew
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############################################################
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puts "--- report_clock_skew ---"
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report_clock_skew -setup
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report_clock_skew -hold
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############################################################
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# All reports with digits
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############################################################
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puts "--- GenClk digits ---"
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report_checks -to [get_ports out2] -path_delay max -format full_clock_expanded -digits 6
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report_checks -to [get_ports out2] -path_delay max -format full_clock_expanded -digits 2
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############################################################
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# report_tns/wns
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############################################################
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puts "--- tns/wns ---"
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report_tns
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report_wns
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report_worst_slack -max
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report_worst_slack -min
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