119 lines
4.4 KiB
C++
119 lines
4.4 KiB
C++
// OpenSTA, Static Timing Analyzer
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// Copyright (c) 2025, Parallax Software, Inc.
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <https://www.gnu.org/licenses/>.
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//
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// The origin of this software must not be misrepresented; you must not
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// claim that you wrote the original software.
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//
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// Altered source versions must be plainly marked as such, and must not be
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// misrepresented as being the original software.
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//
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// This notice may not be removed or altered from any source distribution.
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#include "ParallelDelayCalc.hh"
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#include "TimingArc.hh"
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#include "Corner.hh"
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#include "Network.hh"
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#include "Graph.hh"
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#include "Sdc.hh"
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#include "Liberty.hh"
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#include "GraphDelayCalc.hh"
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namespace sta {
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using std::vector;
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ParallelDelayCalc::ParallelDelayCalc(StaState *sta):
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DelayCalcBase(sta)
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{
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}
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ArcDcalcResultSeq
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ParallelDelayCalc::gateDelays(ArcDcalcArgSeq &dcalc_args,
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const LoadPinIndexMap &load_pin_index_map,
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const DcalcAnalysisPt *dcalc_ap)
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{
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if (dcalc_args.size() == 1) {
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ArcDcalcArg &dcalc_arg = dcalc_args[0];
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ArcDcalcResult dcalc_result = gateDelay(dcalc_arg.drvrPin(), dcalc_arg.arc(),
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dcalc_arg.inSlew(), dcalc_arg.loadCap(),
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dcalc_arg.parasitic(),
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load_pin_index_map, dcalc_ap);
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ArcDcalcResultSeq dcalc_results;
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dcalc_results.push_back(dcalc_result);
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return dcalc_results;
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}
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return gateDelaysParallel(dcalc_args, load_pin_index_map, dcalc_ap);
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}
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ArcDcalcResultSeq
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ParallelDelayCalc::gateDelaysParallel(ArcDcalcArgSeq &dcalc_args,
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const LoadPinIndexMap &load_pin_index_map,
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const DcalcAnalysisPt *dcalc_ap)
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{
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size_t drvr_count = dcalc_args.size();
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ArcDcalcResultSeq dcalc_results(drvr_count);
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Slew slew_sum = 0.0;
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ArcDelay load_delay_sum = 0.0;
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vector<ArcDelay> intrinsic_delays(dcalc_args.size());
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vector<ArcDelay> load_delays(dcalc_args.size());
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for (size_t drvr_idx = 0; drvr_idx < drvr_count; drvr_idx++) {
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ArcDcalcArg &dcalc_arg = dcalc_args[drvr_idx];
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ArcDcalcResult &dcalc_result = dcalc_results[drvr_idx];
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const Pin *drvr_pin = dcalc_arg.drvrPin();
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const TimingArc *arc = dcalc_arg.arc();
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Slew in_slew = dcalc_arg.inSlew();
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ArcDcalcResult intrinsic_result = gateDelay(drvr_pin, arc, in_slew, 0.0, nullptr,
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load_pin_index_map, dcalc_ap);
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ArcDelay intrinsic_delay = intrinsic_result.gateDelay();
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intrinsic_delays[drvr_idx] = intrinsic_result.gateDelay();
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ArcDcalcResult gate_result = gateDelay(drvr_pin, arc, in_slew, dcalc_arg.loadCap(),
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dcalc_arg.parasitic(),
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load_pin_index_map, dcalc_ap);
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ArcDelay gate_delay = gate_result.gateDelay();
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Slew drvr_slew = gate_result.drvrSlew();
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ArcDelay load_delay = gate_delay - intrinsic_delay;
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load_delays[drvr_idx] = load_delay;
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if (!delayZero(load_delay))
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load_delay_sum += 1.0 / load_delay;
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if (!delayZero(drvr_slew))
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slew_sum += 1.0 / drvr_slew;
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dcalc_result.setLoadCount(load_pin_index_map.size());
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for (const auto &[load_pin, load_idx] : load_pin_index_map) {
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dcalc_result.setWireDelay(load_idx, gate_result.wireDelay(load_idx));
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dcalc_result.setLoadSlew(load_idx, gate_result.loadSlew(load_idx));
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}
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}
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ArcDelay gate_load_delay = delayZero(load_delay_sum)
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? delay_zero
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: 1.0 / load_delay_sum;
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ArcDelay drvr_slew = delayZero(slew_sum) ? delay_zero : 1.0 / slew_sum;
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for (size_t drvr_idx = 0; drvr_idx < drvr_count; drvr_idx++) {
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ArcDcalcResult &dcalc_result = dcalc_results[drvr_idx];
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dcalc_result.setGateDelay(intrinsic_delays[drvr_idx] + gate_load_delay);
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dcalc_result.setDrvrSlew(drvr_slew);
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}
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return dcalc_results;
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}
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} // namespace
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