29 lines
1.2 KiB
Tcl
29 lines
1.2 KiB
Tcl
# set_input_delay -reference_pin must survive a graph rebuild that keeps SDC
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# (resizer-like: sta::network_changed_non_sdc deletes the graph but not the
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# constraints). The ref_pin->input graph edge is owned by the graph; its
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# existence flag (PortDelay::ref_pin_edges_exist_) must be reset on graph
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# teardown so ensureInputDelayRefPinEdges() rebuilds the edge. Otherwise in1
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# loses its arrival seeding and reports "No paths found" after the rebuild.
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# in2 is a plain input delay (no ref_pin) used as a control.
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read_liberty asap7_small.lib.gz
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read_verilog reg1_asap7.v
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link_design top
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create_clock -name clk -period 500 {clk1 clk2 clk3}
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set_input_delay -clock clk 100 -reference_pin r2/CLK [get_ports in1]
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set_input_delay -clock clk 100 [get_ports in2]
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set_input_transition 10 {in1 in2 clk1 clk2 clk3}
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set_output_delay -clock clk 1 [get_ports out]
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puts "=== before rebuild: in1 (ref_pin) ==="
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report_checks -from in1 -path_delay max
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puts "=== before rebuild: in2 (control) ==="
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report_checks -from in2 -path_delay max
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sta::network_changed_non_sdc
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puts "=== after rebuild: in1 (ref_pin) ==="
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report_checks -from in1 -path_delay max
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puts "=== after rebuild: in2 (control) ==="
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report_checks -from in2 -path_delay max
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