34 lines
1.4 KiB
Plaintext
34 lines
1.4 KiB
Plaintext
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Slew Delay Time Description
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----------------------------------------------------------------
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0.00 0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock source latency
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10.00 0.00 0.00 ^ clk2 (in)
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48.15 12.04 12.04 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
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38.97 90.82 102.86 ^ r2/Q (DFFHQx4_ASAP7_75t_R)
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59.28 16.50 119.36 ^ u1/A (BUFx2_ASAP7_75t_R)
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70.25 51.69 171.05 ^ u1/Y (BUFx2_ASAP7_75t_R)
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83.74 18.32 189.37 ^ u2/B (AND2x2_ASAP7_75t_R)
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72.19 60.76 250.13 ^ u2/Y (AND2x2_ASAP7_75t_R)
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85.61 18.34 268.46 ^ r3/D (DFFHQx4_ASAP7_75t_R)
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268.46 data arrival time
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0.00 500.00 500.00 clock clk (rise edge)
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0.00 500.00 clock source latency
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10.00 0.00 500.00 ^ clk3 (in)
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47.52 11.84 511.84 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
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0.00 511.84 clock reconvergence pessimism
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-14.89 496.95 library setup time
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496.95 data required time
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----------------------------------------------------------------
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496.95 data required time
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-268.46 data arrival time
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----------------------------------------------------------------
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228.48 slack (MET)
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