16 lines
512 B
Verilog
16 lines
512 B
Verilog
module sdf_test5 (clk, d1, d2, en, q1, q2, q3);
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input clk, d1, d2, en;
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output q1, q2, q3;
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wire n1, n2, n3, n4, n5, n6;
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BUF_X1 buf1 (.A(d1), .Z(n1));
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BUF_X2 buf2 (.A(d2), .Z(n2));
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INV_X1 inv1 (.A(n1), .ZN(n3));
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AND2_X1 and1 (.A1(n1), .A2(n2), .ZN(n4));
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OR2_X1 or1 (.A1(n3), .A2(n4), .ZN(n5));
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NAND2_X1 nand1 (.A1(n5), .A2(en), .ZN(n6));
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DFF_X1 reg1 (.D(n5), .CK(clk), .Q(q1), .QN());
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DFF_X1 reg2 (.D(n6), .CK(clk), .Q(q2), .QN());
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DFF_X1 reg3 (.D(n4), .CK(clk), .Q(q3), .QN());
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endmodule
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