30 lines
1.1 KiB
Tcl
30 lines
1.1 KiB
Tcl
# get_* on object references
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# Read in design and libraries
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read_liberty asap7_small.lib.gz
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read_verilog reg1_asap7.v
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link_design top
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create_clock -name clk -period 500 {clk1 clk2 clk3}
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create_clock -name vclk -period 1000
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# Test that set_driving_cell works with an object reference
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set_driving_cell [all_inputs] -lib_cell [lindex [get_lib_cells] 0]
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# Test each SDC get_* command on object references
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puts {[get_cells [all_registers -cells]]}
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report_object_full_names [get_cells [all_registers -cells]]
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puts {[get_clocks [all_clocks]]}
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report_object_full_names [get_clocks [all_clocks]]
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puts {[get_lib_cells [get_lib_cells]]}
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report_object_full_names [get_lib_cells [get_lib_cells]]
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puts {[get_lib_pins [get_lib_pins]]}
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report_object_full_names [get_lib_pins [get_lib_pins]]
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puts {[get_libs [get_libs]]}
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report_object_full_names [get_libs [get_libs]]
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puts {[get_nets [get_nets]]}
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report_object_full_names [get_nets [get_nets]]
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puts {[get_pins [all_registers -data_pins]]}
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report_object_full_names [get_pins [all_registers -data_pins]]
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puts {[get_ports [all_inputs]]}
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report_object_full_names [get_ports [all_inputs]]
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