OpenSTA/test/report_checks_src_attr.ok

29 lines
1.7 KiB
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Startpoint: _1415_ (rising edge-triggered flip-flop clocked by clk)
Endpoint: _1416_[0] (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Cap Slew Delay Time Description Src Attr
---------------------------------------------------------------------------------------------------------------
0.00 0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 0.00 ^ _1415_/CLK (sky130_fd_sc_hd__dfrtp_1) synthesis/tests/counter.v:22.3-28.6
0.00 0.04 0.33 0.33 v _1415_/Q (sky130_fd_sc_hd__dfrtp_1) synthesis/tests/counter.v:22.3-28.6
mid (net) synthesis/tests/counter.v:22.3-28.6
0.04 0.00 0.33 v _1416_[0]/D (sky130_fd_sc_hd__dfrtp_1) synthesis/tests/counter.v:22.3-28.6
0.33 data arrival time
0.00 10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
10.00 ^ _1416_[0]/CLK (sky130_fd_sc_hd__dfrtp_1)
-0.12 9.88 library setup time
9.88 data required time
---------------------------------------------------------------------------------------------------------------
9.88 data required time
-0.33 data arrival time
---------------------------------------------------------------------------------------------------------------
9.55 slack (MET)