12 lines
368 B
Verilog
12 lines
368 B
Verilog
module top (clk, clkout, data_in, data_out);
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input clk;
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output clkout;
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input [1:0] data_in;
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output [1:0] data_out;
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// Anchor buffers on the source-synchronous interface IOs
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BUFx2_ASAP7_75t_R clkbuf0 (.A(clk), .Y(clkout));
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BUFx2_ASAP7_75t_R u0 (.A(data_in[0]), .Y(data_out[0]));
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BUFx2_ASAP7_75t_R u1 (.A(data_in[1]), .Y(data_out[1]));
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endmodule // top
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