Update goldens for "dcalc no slew merge for constant disabled arcs".
dcalc_case_analysis_leak: arrival spread across the wire-load sweep on the
constant net drops from 46.38 ps to 0.00 ps, which is the point of the test.
Rewrite the header comment to describe the fix rather than the open bug.
graph_modify: with set_case_analysis 0 on d4, inv2 drives n4=1 and or1
drives n6=1, so nand1/A2 is constant. 1 is non-controlling for a NAND, so
nand1/ZN stays live and the A2->ZN arc is dead. Its slew no longer merges
into nand1/ZN, so buf4/Z falls from 0.07 to 0.06. The following report,
after unset_case_analysis, still shows 0.07 as expected.
sdc_port_delay_advanced: in1=0, in2=1 and case analysis 0 on in3 make
nor1/ZN constant, so it is no longer reported as the worst max slew pin;
reg1/QN takes its place.
Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>
5500bdba47