13 lines
361 B
Verilog
13 lines
361 B
Verilog
module top (a, c, z);
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input a, c;
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output z;
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wire cn, n1;
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// set_case_analysis 1 on port c makes net cn constant.
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BUF_X1 u0 (.A(c), .Z(cn));
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// 1 is non-controlling for AND2, so n1 is NOT constant.
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AND2_X1 u1 (.A1(a), .A2(cn), .ZN(n1));
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// Consumes n1's slew, so slew corruption becomes a delay change.
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BUF_X1 u2 (.A(n1), .Z(z));
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endmodule
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