429 lines
15 KiB
C++
429 lines
15 KiB
C++
// OpenSTA, Static Timing Analyzer
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// Copyright (c) 2025, Parallax Software, Inc.
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <https://www.gnu.org/licenses/>.
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//
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// The origin of this software must not be misrepresented; you must not
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// claim that you wrote the original software.
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//
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// Altered source versions must be plainly marked as such, and must not be
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// misrepresented as being the original software.
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//
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// This notice may not be removed or altered from any source distribution.
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#include "DmpDelayCalc.hh"
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#include "TableModel.hh"
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#include "TimingArc.hh"
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#include "Liberty.hh"
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#include "PortDirection.hh"
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#include "Network.hh"
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#include "Sdc.hh"
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#include "Parasitics.hh"
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#include "DcalcAnalysisPt.hh"
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#include "GraphDelayCalc.hh"
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#include "DmpCeff.hh"
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namespace sta {
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// PiElmore parasitic delay calculator using Dartu/Menezes/Pileggi
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// effective capacitance and elmore delay.
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class DmpCeffElmoreDelayCalc : public DmpCeffDelayCalc
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{
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public:
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DmpCeffElmoreDelayCalc(StaState *sta);
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ArcDelayCalc *copy() override;
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const char *name() const override { return "dmp_ceff_elmore"; }
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ArcDcalcResult inputPortDelay(const Pin *port_pin,
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float in_slew,
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const RiseFall *rf,
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const Parasitic *parasitic,
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const LoadPinIndexMap &load_pin_index_map,
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const DcalcAnalysisPt *dcalc_ap) override;
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protected:
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void loadDelaySlew(const Pin *load_pin,
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double drvr_slew,
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const RiseFall *rf,
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const LibertyLibrary *drvr_library,
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const Parasitic *parasitic,
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// Return values.
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ArcDelay &wire_delay,
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Slew &load_slew) override;
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};
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ArcDelayCalc *
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makeDmpCeffElmoreDelayCalc(StaState *sta)
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{
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return new DmpCeffElmoreDelayCalc(sta);
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}
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DmpCeffElmoreDelayCalc::DmpCeffElmoreDelayCalc(StaState *sta) :
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DmpCeffDelayCalc(sta)
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{
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}
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ArcDelayCalc *
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DmpCeffElmoreDelayCalc::copy()
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{
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return new DmpCeffElmoreDelayCalc(this);
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}
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ArcDcalcResult
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DmpCeffElmoreDelayCalc::inputPortDelay(const Pin *,
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float in_slew,
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const RiseFall *rf,
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const Parasitic *parasitic,
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const LoadPinIndexMap &load_pin_index_map,
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const DcalcAnalysisPt *)
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{
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ArcDcalcResult dcalc_result(load_pin_index_map.size());
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LibertyLibrary *drvr_library = network_->defaultLibertyLibrary();
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for (auto [load_pin, load_idx] : load_pin_index_map) {
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ArcDelay wire_delay = 0.0;
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Slew load_slew = in_slew;
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bool elmore_exists = false;
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float elmore = 0.0;
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if (parasitic)
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parasitics_->findElmore(parasitic, load_pin, elmore, elmore_exists);
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if (elmore_exists)
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// Input port with no external driver.
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dspfWireDelaySlew(load_pin, rf, in_slew, elmore, wire_delay, load_slew);
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thresholdAdjust(load_pin, drvr_library, rf, wire_delay, load_slew);
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dcalc_result.setWireDelay(load_idx, wire_delay);
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dcalc_result.setLoadSlew(load_idx, load_slew);
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}
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return dcalc_result;
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}
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void
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DmpCeffElmoreDelayCalc::loadDelaySlew(const Pin *load_pin,
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double drvr_slew,
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const RiseFall *rf,
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const LibertyLibrary *drvr_library,
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const Parasitic *parasitic,
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// Return values.
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ArcDelay &wire_delay,
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Slew &load_slew)
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{
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wire_delay = 0.0;
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load_slew = drvr_slew;
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bool elmore_exists = false;
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float elmore = 0.0;
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if (parasitic)
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parasitics_->findElmore(parasitic, load_pin, elmore, elmore_exists);
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if (elmore_exists)
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loadDelaySlewElmore(load_pin, elmore, wire_delay, load_slew);
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thresholdAdjust(load_pin, drvr_library, rf, wire_delay, load_slew);
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}
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////////////////////////////////////////////////////////////////
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// PiPoleResidue parasitic delay calculator using Dartu/Menezes/Pileggi
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// effective capacitance and two poles/residues.
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class DmpCeffTwoPoleDelayCalc : public DmpCeffDelayCalc
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{
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public:
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DmpCeffTwoPoleDelayCalc(StaState *sta);
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ArcDelayCalc *copy() override;
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const char *name() const override { return "dmp_ceff_two_pole"; }
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Parasitic *findParasitic(const Pin *drvr_pin,
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const RiseFall *rf,
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const DcalcAnalysisPt *dcalc_ap) override;
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ArcDcalcResult inputPortDelay(const Pin *port_pin,
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float in_slew,
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const RiseFall *rf,
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const Parasitic *parasitic,
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const LoadPinIndexMap &load_pin_index_map,
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const DcalcAnalysisPt *dcalc_ap) override;
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ArcDcalcResult gateDelay(const Pin *drvr_pin,
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const TimingArc *arc,
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const Slew &in_slew,
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float load_cap,
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const Parasitic *parasitic,
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const LoadPinIndexMap &load_pin_index_map,
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const DcalcAnalysisPt *dcalc_ap) override;
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private:
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void loadDelaySlew(const Pin *load_pin,
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double drvr_slew,
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const RiseFall *rf,
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const LibertyLibrary *drvr_library,
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const Parasitic *parasitic,
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// Return values.
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ArcDelay &wire_delay,
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Slew &load_slew) override;
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void loadDelay(double drvr_slew,
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Parasitic *pole_residue,
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double p1,
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double k1,
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ArcDelay &wire_delay,
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Slew &load_slew);
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float loadDelay(double vth,
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double p1,
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double p2,
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double k1,
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double k2,
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double B,
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double k1_p1_2,
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double k2_p2_2,
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double tt,
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double y_tt);
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bool parasitic_is_pole_residue_;
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float vth_;
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float vl_;
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float vh_;
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float slew_derate_;
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};
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ArcDelayCalc *
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makeDmpCeffTwoPoleDelayCalc(StaState *sta)
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{
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return new DmpCeffTwoPoleDelayCalc(sta);
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}
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DmpCeffTwoPoleDelayCalc::DmpCeffTwoPoleDelayCalc(StaState *sta) :
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DmpCeffDelayCalc(sta),
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parasitic_is_pole_residue_(false),
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vth_(0.0),
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vl_(0.0),
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vh_(0.0),
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slew_derate_(0.0)
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{
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}
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ArcDelayCalc *
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DmpCeffTwoPoleDelayCalc::copy()
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{
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return new DmpCeffTwoPoleDelayCalc(this);
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}
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Parasitic *
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DmpCeffTwoPoleDelayCalc::findParasitic(const Pin *drvr_pin,
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const RiseFall *rf,
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const DcalcAnalysisPt *dcalc_ap)
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{
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Parasitic *parasitic = nullptr;
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const Corner *corner = dcalc_ap->corner();
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// set_load net has precedence over parasitics.
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if (sdc_->drvrPinHasWireCap(drvr_pin, corner)
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|| network_->direction(drvr_pin)->isInternal())
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return nullptr;
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const ParasiticAnalysisPt *parasitic_ap = dcalc_ap->parasiticAnalysisPt();
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// Prefer PiPoleResidue.
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parasitic = parasitics_->findPiPoleResidue(drvr_pin, rf, parasitic_ap);
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if (parasitic)
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return parasitic;
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parasitic = parasitics_->findPiElmore(drvr_pin, rf, parasitic_ap);
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if (parasitic)
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return parasitic;
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Parasitic *parasitic_network =
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parasitics_->findParasiticNetwork(drvr_pin, parasitic_ap);
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if (parasitic_network) {
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parasitic = parasitics_->reduceToPiPoleResidue2(parasitic_network, drvr_pin, rf,
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corner,
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dcalc_ap->constraintMinMax(),
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parasitic_ap);
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if (parasitic)
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return parasitic;
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}
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const MinMax *cnst_min_max = dcalc_ap->constraintMinMax();
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Wireload *wireload = sdc_->wireload(cnst_min_max);
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if (wireload) {
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float pin_cap, wire_cap, fanout;
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bool has_wire_cap;
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graph_delay_calc_->netCaps(drvr_pin, rf, dcalc_ap, pin_cap, wire_cap,
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fanout, has_wire_cap);
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parasitic = parasitics_->estimatePiElmore(drvr_pin, rf, wireload,
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fanout, pin_cap, corner,
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cnst_min_max);
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}
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return parasitic;
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}
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ArcDcalcResult
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DmpCeffTwoPoleDelayCalc::inputPortDelay(const Pin *,
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float in_slew,
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const RiseFall *rf,
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const Parasitic *parasitic,
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const LoadPinIndexMap &load_pin_index_map,
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const DcalcAnalysisPt *)
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{
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ArcDcalcResult dcalc_result(load_pin_index_map.size());
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ArcDelay wire_delay = 0.0;
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Slew load_slew = in_slew;
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LibertyLibrary *drvr_library = network_->defaultLibertyLibrary();
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for (const auto [load_pin, load_idx] : load_pin_index_map) {
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if (parasitics_->isPiPoleResidue(parasitic)) {
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const Parasitic *pole_residue = parasitics_->findPoleResidue(parasitic, load_pin);
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if (pole_residue) {
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size_t pole_count = parasitics_->poleResidueCount(pole_residue);
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if (pole_count >= 1) {
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ComplexFloat pole1, residue1;
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// Find the 1st (elmore) pole.
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parasitics_->poleResidue(pole_residue, 0, pole1, residue1);
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if (pole1.imag() == 0.0
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&& residue1.imag() == 0.0) {
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float p1 = pole1.real();
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float elmore = 1.0F / p1;
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dspfWireDelaySlew(load_pin, rf, in_slew, elmore, wire_delay, load_slew);
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thresholdAdjust(load_pin, drvr_library, rf, wire_delay, load_slew);
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}
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}
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}
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}
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dcalc_result.setWireDelay(load_idx, wire_delay);
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dcalc_result.setLoadSlew(load_idx, load_slew);
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}
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return dcalc_result;
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}
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ArcDcalcResult
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DmpCeffTwoPoleDelayCalc::gateDelay(const Pin *drvr_pin,
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const TimingArc *arc,
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const Slew &in_slew,
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float load_cap,
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const Parasitic *parasitic,
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const LoadPinIndexMap &load_pin_index_map,
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const DcalcAnalysisPt *dcalc_ap)
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{
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const LibertyLibrary *drvr_library = arc->to()->libertyLibrary();
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const RiseFall *rf = arc->toEdge()->asRiseFall();
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vth_ = drvr_library->outputThreshold(rf);
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vl_ = drvr_library->slewLowerThreshold(rf);
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vh_ = drvr_library->slewUpperThreshold(rf);
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slew_derate_ = drvr_library->slewDerateFromLibrary();
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return DmpCeffDelayCalc::gateDelay(drvr_pin, arc, in_slew, load_cap, parasitic,
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load_pin_index_map, dcalc_ap) ;
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}
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void
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DmpCeffTwoPoleDelayCalc::loadDelaySlew(const Pin *load_pin,
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double drvr_slew,
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const RiseFall *rf,
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const LibertyLibrary *drvr_library,
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const Parasitic *parasitic,
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// Return values.
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ArcDelay &wire_delay,
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Slew &load_slew)
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{
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parasitic_is_pole_residue_ = parasitics_->isPiPoleResidue(parasitic);
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// Should handle PiElmore parasitic.
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wire_delay = 0.0;
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load_slew = drvr_slew;
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Parasitic *pole_residue = 0;
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if (parasitic_is_pole_residue_)
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pole_residue = parasitics_->findPoleResidue(parasitic, load_pin);
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if (pole_residue) {
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size_t pole_count = parasitics_->poleResidueCount(pole_residue);
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if (pole_count >= 1) {
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ComplexFloat pole1, residue1;
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// Find the 1st (elmore) pole.
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parasitics_->poleResidue(pole_residue, 0, pole1, residue1);
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if (pole1.imag() == 0.0
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&& residue1.imag() == 0.0) {
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float p1 = pole1.real();
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float k1 = residue1.real();
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if (pole_count >= 2)
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loadDelay(drvr_slew, pole_residue, p1, k1, wire_delay, load_slew);
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else {
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float elmore = 1.0F / p1;
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wire_delay = elmore;
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load_slew = drvr_slew;
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}
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}
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}
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}
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thresholdAdjust(load_pin, drvr_library, rf, wire_delay, load_slew);
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}
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void
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DmpCeffTwoPoleDelayCalc::loadDelay(double drvr_slew,
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Parasitic *pole_residue,
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double p1,
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double k1,
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// Return values.
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ArcDelay &wire_delay,
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Slew &load_slew)
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{
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ComplexFloat pole2, residue2;
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parasitics_->poleResidue(pole_residue, 1, pole2, residue2);
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if (!delayZero(drvr_slew)
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&& pole2.imag() == 0.0
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&& residue2.imag() == 0.0) {
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double p2 = pole2.real();
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double k2 = residue2.real();
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double k1_p1_2 = k1 / (p1 * p1);
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double k2_p2_2 = k2 / (p2 * p2);
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double B = k1_p1_2 + k2_p2_2;
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// Convert tt to 0:1 range.
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float tt = delayAsFloat(drvr_slew) * slew_derate_ / (vh_ - vl_);
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double y_tt = (tt - B + k1_p1_2 * exp(-p1 * tt)
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+ k2_p2_2 * exp(-p2 * tt)) / tt;
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wire_delay = loadDelay(vth_, p1, p2, k1, k2, B, k1_p1_2, k2_p2_2, tt, y_tt)
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- tt * vth_;
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float tl = loadDelay(vl_, p1, p2, k1, k2, B, k1_p1_2, k2_p2_2, tt, y_tt);
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float th = loadDelay(vh_, p1, p2, k1, k2, B, k1_p1_2, k2_p2_2, tt, y_tt);
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load_slew = (th - tl) / slew_derate_;
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}
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}
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float
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DmpCeffTwoPoleDelayCalc::loadDelay(double vth,
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double p1,
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double p2,
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double k1,
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double k2,
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double B,
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double k1_p1_2,
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double k2_p2_2,
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double tt,
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double y_tt)
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{
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if (y_tt < vth) {
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// t1 > tt
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// Initial guess.
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double t1 = log(k1 * (exp(p1 * tt) - 1.0) / ((1.0 - vth) * p1 * p1 * tt))/p1;
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// Take one newton-raphson step.
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double exp_p1_t1 = exp(-p1 * t1);
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double exp_p2_t1 = exp(-p2 * t1);
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double exp_p1_t1_tt = exp(-p1 * (t1 - tt));
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double exp_p2_t1_tt = exp(-p2 * (t1 - tt));
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double y_t1 = (tt - k1_p1_2 * (exp_p1_t1_tt - exp_p1_t1)
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- k2_p2_2 * (exp_p2_t1_tt - exp_p2_t1)) / tt;
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double yp_t1 = (k1 / p1 * (exp_p1_t1_tt - exp_p1_t1)
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- k2 / p2 * (exp_p2_t1_tt - exp_p2_t1)) / tt;
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double delay = t1 - (y_t1 - vth) / yp_t1;
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return static_cast<float>(delay);
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}
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else {
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// t1 < tt
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// Initial guess based on y(tt).
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double t1 = vth * tt / y_tt;
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// Take one newton-raphson step.
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double exp_p1_t1 = exp(-p1 * t1);
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double exp_p2_t1 = exp(-p2 * t1);
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double y_t1 = (t1 - B + k1_p1_2 * exp_p1_t1
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+ k2_p2_2 * exp_p1_t1) / tt;
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double yp_t1 = (1 - k1 / p1 * exp_p1_t1
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- k2 / p2 * exp_p2_t1) / tt;
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double delay = t1 - (y_t1 - vth) / yp_t1;
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return static_cast<float>(delay);
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}
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}
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} // namespace
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