Deepashree Sengupta
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eb0446d4e2
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Write verilog escape (#394)
* Fir for write_verilog issue 3826
Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>
* staToVerilog2 remove escaped_name+=ch
Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>
* updated regression to remove \ from module name
Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>
* Using helpers.tcl function to redirect results
Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>
* add std::string and remove trailing space, update regression name
Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>
* update regression to reflect correct output verilog name
Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>
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Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>
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2026-03-02 16:48:15 -08:00 |