6 Commits

Author	SHA1	Message	Date
James Cherry	74e287a7eb	write_verilog escaped bus port name "input [7:0] \in[0] ;"	2019-07-03 21:18:38 -07:00
James Cherry	eea6ab1a29	write_verilog -sorted -> -sort	2019-06-17 12:33:37 -07:00
James Cherry	49b2c3cea7	rm redundant StaState args	2019-06-17 08:32:28 -07:00
James Cherry	3f7e207491	write_verilog	2019-06-16 21:08:00 -07:00
James Cherry	b075ccc783	update copyright	2019-01-01 12:26:11 -08:00
James Cherry	1154fb89fd	and then there was light...	2018-09-28 08:54:21 -07:00