c887b2e4b3
Bias pin handling ( #409 )
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* Update STA to exclude bias pins from timing graph and subsequently in write_verilog
Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>
* unnecessary space in orig verilog
Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>
* Update to use well supplies rather than bias pins
Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>
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Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>
2026-04-07 11:00:01 -07:00
6742692876
string squash
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Signed-off-by: James Cherry <cherry@parallaxsw.com>
2026-03-28 19:13:35 -07:00
981f44db68
update copyright
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Signed-off-by: James Cherry <cherry@parallaxsw.com>
2026-03-10 14:57:45 -07:00
d42b821c00
rel 3.0
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Signed-off-by: James Cherry <cherry@parallaxsw.com>
2026-01-13 09:36:45 -07:00
2a4fd08211
update copyright
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Signed-off-by: James Cherry <cherry@parallaxsw.com>
2025-01-21 18:54:33 -07:00
422a5819bd
update copyright
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Signed-off-by: James Cherry <cherry@parallaxsw.com>
2024-01-11 16:34:49 -08:00
ef43ee9a45
make_port
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Signed-off-by: James Cherry <cherry@parallaxsw.com>
2023-06-28 10:01:39 -07:00
cc2ef1783f
update copyright
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Signed-off-by: James Cherry <cherry@parallaxsw.com>
2023-02-18 17:55:40 -07:00
bbf5584e30
flush DISALLOW_COPY_AND_ASSIGN
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Signed-off-by: James Cherry <cherry@parallaxsw.com>
2022-02-19 18:31:52 -07:00
2bc6e8f68c
update copyright
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Signed-off-by: James Cherry <cherry@parallaxsw.com>
2022-01-04 10:17:08 -07:00
ee326f165c
public headers in include/sta
2020-04-05 14:53:44 -07:00
Deepashree Sengupta
James Cherry