5 Commits

Author	SHA1	Message	Date
James Cherry	3d8d088b89	sync	2019-01-05 16:09:27 -08:00
James Cherry	b075ccc783	update copyright	2019-01-01 12:26:11 -08:00
James Cherry	e1059eac12	find_timing_paths	2018-12-20 22:41:54 -08:00
James Cherry	e9bde796ec	2018/11/08 corners > 2 causes internal error, 2018/11/09 Verilog ignore attributes (* blah *)	2018-11-09 10:04:16 -08:00
James Cherry	1154fb89fd	and then there was light...	2018-09-28 08:54:21 -07:00