James Cherry
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e2d02839a3
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examples
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2019-03-21 10:48:50 -07:00 |
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James Cherry
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e5c9bc43fd
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2.0.10
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2019-03-12 17:25:53 -07:00 |
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James Cherry
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1af0963fd4
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2019/02/21 write_path_spice include side load pins
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2019-02-21 08:00:06 -08:00 |
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James Cherry
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cb3ba357bb
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write_path_spice first line is comment
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2019-02-18 22:32:59 -08:00 |
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James Cherry
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d8146af755
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remove autotools/configure support
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2019-02-16 12:07:59 -08:00 |
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James Cherry
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316742202f
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sync
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2019-01-16 15:37:31 -08:00 |
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James Cherry
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b0d30fed3c
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2019/01/07 WritePathSpice don't barf on spice subckts missing liberty cells
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2019-01-07 22:15:17 -08:00 |
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James Cherry
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3d8d088b89
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sync
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2019-01-05 16:09:27 -08:00 |
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James Cherry
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de5c3a6400
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write_path_spice write multiple paths
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2019-01-03 22:31:59 -08:00 |
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James Cherry
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9e5aac37f4
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cmake, write_path_spice
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2019-01-03 16:14:15 -08:00 |
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James Cherry
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b075ccc783
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update copyright
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2019-01-01 12:26:11 -08:00 |
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James Cherry
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9435640d5a
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write_spice alpha
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2019-01-01 12:25:25 -08:00 |
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James Cherry
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a6e21377e6
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2.0.2
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2018-12-26 11:03:31 -08:00 |
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James Cherry
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d29d66c7fb
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INSTALL
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2018-12-15 14:40:22 -08:00 |
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James Cherry
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3c0d8c7002
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dist
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2018-12-15 11:08:24 -08:00 |
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James Cherry
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f49dc75d32
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sync
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2018-12-05 14:18:41 -08:00 |
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James Cherry
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c3b1679bd7
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OpenSTA.pdf
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2018-11-26 11:42:25 -08:00 |
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James Cherry
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ddf897d4e6
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report_power, pocv support
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2018-11-26 09:15:52 -08:00 |
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James Cherry
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e9bde796ec
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2018/11/08 corners > 2 causes internal error, 2018/11/09 Verilog ignore attributes (* blah *)
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2018-11-09 10:04:16 -08:00 |
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James Cherry
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2af22d9331
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2018/10/23 read_verilog mod inst with no ports seg fault
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2018-10-23 16:24:22 -07:00 |
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James Cherry
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1154fb89fd
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and then there was light...
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2018-09-28 08:54:21 -07:00 |