power activity thru regs caps at 1/clk_period

Signed-off-by: James Cherry <cherry@parallaxsw.com>

include/sta/PowerClass.hh

@@ -38,7 +38,9 @@ public:
 	      float duty,
 	      PwrActivityOrigin origin);
   float activity() const { return activity_; }
+  void setActivity(float activity);
   float duty() const { return duty_; }
+  void setDuty(float duty);
   PwrActivityOrigin origin() { return origin_; }
   const char *originName() const;
   void set(float activity,

power/Power.cc

@@ -572,10 +572,13 @@ Power::seedRegOutputActivities(const Instance *reg,
   const Pin *out_pin = network_->findPin(reg, output);
   if (!hasUserActivity(out_pin)) {
     PwrActivity activity = evalActivity(seq->data(), reg);
+    // Register output activity cannnot exceed one transition per clock cycle,
+    // but latch output can.
+    if (seq->isRegister()
+        && activity.activity() > 1.0)
+      activity.setActivity(1.0);
     if (invert)
-      activity.set(activity.activity(),
+      activity.setDuty(1.0 - activity.duty());
-                   1.0 - activity.duty(),
-                   activity.origin());
     setSeqActivity(reg, output, activity);
   }
 }
@@ -1190,6 +1193,18 @@ PwrActivity::PwrActivity() :
   check();
 }
 
+void
+PwrActivity::setActivity(float activity)
+{
+  activity_ = activity;
+}
+
+void
+PwrActivity::setDuty(float duty)
+{
+  duty_ = duty;
+}
+
 void
 PwrActivity::set(float activity,
 		 float duty,