Merge remote-tracking branch 'parallax/master'

Get the CCS update

Signed-off-by: Matt Liberty <[email protected]>

include/sta/ArcDelayCalc.hh

@@ -72,6 +72,7 @@ public:
   Edge *edge() const { return edge_; }
   const TimingArc *arc() const { return arc_; }
   Slew inSlew() const { return in_slew_; }
+  float inSlewFlt() const;
   void setInSlew(Slew in_slew);
   const Parasitic *parasitic() { return parasitic_; }
   void setParasitic(const Parasitic *parasitic);

include/sta/Graph.hh

@@ -46,7 +46,6 @@ typedef ArrayTable<Required> RequiredsTable;
 typedef ArrayTable<PathVertexRep> PrevPathsTable;
 typedef Map<const Pin*, Vertex*> PinVertexMap;
 typedef Iterator<Edge*> VertexEdgeIterator;
-typedef Map<const Pin*, float*> WidthCheckAnnotations;
 typedef Map<const Pin*, float*> PeriodCheckAnnotations;
 typedef Vector<DelayTable*> DelayTableSeq;
 typedef ObjectId EdgeId;
@@ -184,18 +183,11 @@ public:
   int edgeCount() { return edges_->size(); }
   virtual int arcCount() { return arc_count_; }
 
-  // Sdf width check annotation.
-  void widthCheckAnnotation(const Pin *pin,
-			    const RiseFall *rf,
-			    DcalcAPIndex ap_index,
-			    // Return values.
-			    float &width,
-			    bool &exists);
-  void setWidthCheckAnnotation(const Pin *pin,
-			       const RiseFall *rf,
-			       DcalcAPIndex ap_index,
-			       float width);
-
+  void minPulseWidthArc(Vertex *vertex,
+                        const RiseFall *hi_low,
+                        // Return values.
+                        Edge *&edge,
+                        TimingArc *&arc);
   // Sdf period check annotation.
   void periodCheckAnnotation(const Pin *pin,
 			     DcalcAPIndex ap_index,
@@ -229,7 +221,6 @@ protected:
   virtual void makePortInstanceEdges(const Instance *inst,
 				     LibertyCell *cell,
                                      LibertyPort *from_to_port);
-  void removeWidthCheckAnnotations();
   void removePeriodCheckAnnotations();
   void makeSlewTables(DcalcAPIndex count);
   void deleteSlewTables();
@@ -264,8 +255,6 @@ protected:
   DelayTableSeq slew_tables_;	      // [ap_index][tr_index][vertex_id]
   VertexId slew_count_;
   DelayTableSeq arc_delays_;	      // [ap_index][edge_arc_index]
-  // Sdf width check annotations.
-  WidthCheckAnnotations *width_check_annotations_;
   // Sdf period check annotations.
   PeriodCheckAnnotations *period_check_annotations_;
   // Register/latch clock vertices to search from.

include/sta/GraphDelayCalc.hh

@@ -109,17 +109,6 @@ public:
   // Precedence:
   //  SDF annotation
   //  Liberty library
-  // (ignores set_min_pulse_width constraint)
-  void minPulseWidth(const Pin *pin,
-		     const RiseFall *hi_low,
-		     DcalcAPIndex ap_index,
-		     const MinMax *min_max,
-		     // Return values.
-		     float &min_width,
-		     bool &exists);
-  // Precedence:
-  //  SDF annotation
-  //  Liberty library
   void minPeriod(const Pin *pin,
 		 // Return values.
 		 float &min_period,

include/sta/Liberty.hh

@@ -728,17 +728,12 @@ public:
   void minPeriod(float &min_period,
 		 bool &exists) const;
   void setMinPeriod(float min_period);
+  // This corresponds to the min_pulse_width_high/low port attribute.
   // high = rise, low = fall
   void minPulseWidth(const RiseFall *hi_low,
-		     const OperatingConditions *op_cond,
-		     const Pvt *pvt,
 		     float &min_width,
 		     bool &exists) const;
-  // Unscaled value.
-  void minPulseWidth(const RiseFall *hi_low,
-		     float &min_width,
-		     bool &exists) const;
-  void setMinPulseWidth(RiseFall *hi_low,
+  void setMinPulseWidth(const RiseFall *hi_low,
 			float min_width);
   bool isClock() const;
   void setIsClock(bool is_clk);

include/sta/PathEnd.hh

@@ -143,7 +143,7 @@ public:
   // PathEndDataCheck data clock path.
   virtual const PathVertex *dataClkPath() const { return nullptr; }
   virtual int setupDefaultCycles() const { return 1; }
-  virtual float clkSkew(const StaState *sta);
+  virtual Delay clkSkew(const StaState *sta);
 
   static bool less(const PathEnd *path_end1,
 		   const PathEnd *path_end2,
@@ -328,7 +328,7 @@ public:
   virtual int exceptPathCmp(const PathEnd *path_end,
 			    const StaState *sta) const;
   virtual Delay sourceClkDelay(const StaState *sta) const;
-  virtual float clkSkew(const StaState *sta);
+  virtual Delay clkSkew(const StaState *sta);
 
 protected:
   PathEndCheck(Path *path,

include/sta/Sdc.hh

@@ -445,6 +445,8 @@ public:
 			 float delay);
   void removeClockInsertion(const Clock *clk,
 			    const Pin *pin);
+  static void moveClockInsertions(Sdc *from,
+                                  Sdc *to);
   bool hasClockInsertion(const Pin *pin) const;
   float clockInsertion(const Clock *clk,
 		       const RiseFall *rf,
@@ -1066,7 +1068,7 @@ protected:
   virtual void recordPathDelayInternalEndpoints(ExceptionPath *exception);
   virtual void unrecordPathDelayInternalEndpoints(ExceptionPath *exception);
   bool pathDelayTo(const Pin *pin);
-  bool hasLibertyChecks(const Pin *pin);
+  bool hasLibertyCheckTo(const Pin *pin);
   void deleteMatchingExceptions(ExceptionPath *exception);
   void findMatchingExceptions(ExceptionPath *exception,
 			      ExceptionPathSet &matches);

include/sta/TimingRole.hh

@@ -65,6 +65,8 @@ public:
   int index() const { return index_; }
   bool isWire() const;
   bool isTimingCheck() const { return is_timing_check_; }
+  // TIming check but not width or period.
+  bool isTimingCheckBetween() const;
   bool isAsyncTimingCheck() const;
   bool isNonSeqTimingCheck() const { return is_non_seq_check_; }
   bool isDataCheck() const;