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write_verilog port missing net (issue 429) 

Signed-off-by: James Cherry <cherry@parallaxsw.com>
This commit is contained in:
James Cherry 2026-05-01 11:34:15 -07:00
parent bd1cbefcd5
commit f813d949ae
1 changed files with 3 additions and 2 deletions
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5
verilog/VerilogWriter.cc
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@ -447,12 +447,13 @@ VerilogWriter::writeAssigns(const Instance *inst)
if (term) {
Net *net = network_->net(term);
Port *port = network_->port(pin);
if (port
if (net
&& port
&& (include_pwr_gnd_
|| !(network_->isPower(net) || network_->isGround(net)))
&& (network_->direction(port)->isAnyOutput()
|| (include_pwr_gnd_ && network_->direction(port)->isPowerGround()))
&& !stringEqual(network_->name(port), network_->name(net))) {
&& network_->name(port) != network_->name(net)) {
// Port name is different from net name.
std::string port_vname = netVerilogName(std::string(network_->name(port)));
std::string net_vname = netVerilogName(std::string(network_->name(net)));