write_timing_model

Signed-off-by: James Cherry <[email protected]>

include/sta/Liberty.hh

@@ -27,6 +27,7 @@
 
 namespace sta {
 
+class WriteTimingModel;
 class LibertyCellIterator;
 class LibertyCellPortIterator;
 class LibertyCellPortBitIterator;
@@ -644,6 +645,7 @@ public:
   LibertyLibrary *libertyLibrary() const { return liberty_cell_->libertyLibrary(); }
   LibertyPort *findLibertyMember(int index) const;
   LibertyPort *findLibertyBusBit(int index) const;
+  void setDirection(PortDirection *dir);
   void fanoutLoad(// Return values.
 		  float &fanout_load,
 		  bool &exists) const;
@@ -769,7 +771,6 @@ protected:
 	      bool is_bundle,
 	      ConcretePortSeq *members);
   virtual ~LibertyPort();
-  void setDirection(PortDirection *dir);
   void setMinPort(LibertyPort *min);
   void addScaledPort(OperatingConditions *op_cond,
 		     LibertyPort *scaled_port);

include/sta/LibertyWriter.hh

@@ -28,5 +28,3 @@ writeLiberty(LibertyLibrary *lib,
              StaState *sta);
 
 } // namespace
-
-

include/sta/Sta.hh

@@ -1267,6 +1267,10 @@ public:
 	     // Return values.
 	     PowerResult &result);
 
+  void writeTimingModel(const char *cell_name,
+                        const char *filename,
+                        const Corner *corner);
+
   // Find equivalent cells in equiv_libs.
   // Optionally add mappings for cells in map_libs.
   void makeEquivCells(LibertyLibrarySeq *equiv_libs,